TC5563APL-12中文資料東芝數(shù)據(jù)手冊(cè)PDF規(guī)格書

DESCRIPTION

The TC5563APL is 65,536 bit static random

access memory organized as 8, 192 words by 8 bits

using CMOS technology, and operates from a single

5V supply. Advanced circuit techniques provide both

high speed and low power features with a maximum

operating current of 5mA/MHz and maximum

access time of 100ns/120ns/150ns.

When CE2 is a logical low or CE1 is a logical high,

the device is placed in low power standby mode in

which standby current is 2μA typically. The

TC5563APL has three control inputs. Two chip

enables (CE1, CE2) allow for device selection and

data retention control, and an output enable input

(OE) provides fast memory access. Thus the

TC5563APL is suitable for use in various micro-

processor application systems where high speed,

low power, and battery back up are required.

The TC5563APL also features pin compatibility

with the 64k bit EPROM (TMM2764D). RAM and

EPROM are then interchangeable in the same

socket, resulting in flexibility in the definition of the

quantity of RAM versus EPROM in microprocessor

application systems.

The TC5563APL is offered in a dual-in-line 28 pin

0.3 inch width plastic package.

FEATURES

Low Power Dissipation

27.5mW/MHz (Max.) Operating

Standby Current: 100μA (Max.) Ta=70°C

Access Time

TC5563APL-10: 100ns (Max.)

TC5563APL-12:

120ns (Max.)

TC5563APL-15:

150ns (Max.)

5V Single Power Supply

Power Down Features: CE2, CE1

Fully Static Operation

Data Retention Supply Voltage: 2.0-5.5V

Directly TTL Compatible

All Inputs and Outputs

Pin Compatible with 2764 type EPROM

TC5565APL Family (Package Type)