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SL74HCT573D中文資料SLS數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)
| 廠商型號(hào) |
SL74HCT573D |
| 功能描述 | Octal 3-State Noninverting Transparent Latch(High-Performance Silicon-Gate CMOS) |
| 文件大小 |
54.45 Kbytes |
| 頁(yè)面數(shù)量 |
6 頁(yè) |
| 生產(chǎn)廠商 | System Logic Semiconductor |
| 企業(yè)簡(jiǎn)稱(chēng) |
SLS |
| 中文名稱(chēng) | System Logic Semiconductor官網(wǎng) |
| 原廠標(biāo)識(shí) |  |
| 數(shù)據(jù)手冊(cè) | |
| 更新時(shí)間 | 2025-1-15 14:53:00 |
SL74HCT573D規(guī)格書(shū)詳情
Octal 3-State Noninverting Transparent Latch
High-Performance Silicon-Gate CMOS
The SL74HCT573 is identical in pinout to the LS/ALS573. This device may be used as a level converter for interfacing TTL or NMOS outputs to High-Speed CMOS inputs.
These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. When Latch Enable goes low, data meeting the setup and hold time becomes latched.
The Output Enable input does not affect the state of the latches, but when Output Enable is high, all device outputs are forced to the high-impedance state. Thus, data may be latched even when the outputs are not enabled.
? TTL/NMOS-Compatible Input Levels
? Outputs Directly Interface to CMOS, NMOS, and TTL
? Operating Voltage Range: 4.5 to 5.5 V
? Low Input Current: 1.0 μA
產(chǎn)品屬性
- 型號(hào)：
SL74HCT573D
- 制造商：
SLS
- 制造商全稱(chēng)：
System Logic Semiconductor
- 功能描述：
Octal 3-State Noninverting Transparent Latch(High-Performance Silicon-Gate CMOS)
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TI |
23+ |
NA |
1335 |
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SLS |
24+ |
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990000 |
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22+ |
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16900 |
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30000 |
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HYNIX |
24+ |
SOP-7.2-20P |
4897 |
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24+ |
3000 |
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DIP-24 |
36900 |
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23+ |
SOP14 |
6850 |
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SLS |
2023+ |
SOP |
80000 |
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MOT |
24+ |
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968 |
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