PZ3064-10A68中文資料飛利浦數(shù)據(jù)手冊PDF規(guī)格書

DESCRIPTION

The PZ3064 CPLD (Complex Programmable Logic Device) is the second in a family of Fast Zero Power (FZP) CPLDs from Philips Semiconductors.

FEATURES

?Industry’s first TotalCMOS?PLD – both CMOS design and process technologies

?Fast Zero Power (FZP?) design technique provides ultra-low power and very high speed

?High speed pin-to-pin delays of 10ns

?Ultra-low static power of less than 50μA

?Dynamic power that is 70 lower at 50MHz than competing devices

?100 routable with 100 utilization while all pins and all macrocells are fixed

?Deterministic timing model that is extremely simple to use

?4 clocks with programmable polarity at every macrocell

?Support for complex asynchronous clocking

?Innovative XPLA?architecture combines high speed with extreme flexibility

?1000 erase/program cycles guaranteed

?20 years data retention guaranteed

?Logic expandable to 37 product terms

?PCI compliant

?Advanced 0.5μE2 CMOS process

?Security bit prevents unauthorized access

?Design entry and verification using industry standard and Philips CAE tools

?Reprogrammable using industry standard device programmers

?Innovative Control Term structure provides either sum terms or product terms in each logic block for:

–Programmable 3-State buffer

–Asynchronous macrocell register preset/reset

?Programmable global 3-State pin facilitates ‘bed of nails’ testing without using logic resources

?Available in PLCC, TQFP, and PQFP packages

?Available in both Commercial and Industrial grades