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PLL102-10SC中文資料PLL數據手冊PDF規(guī)格書

PLL102-10SC
廠商型號

PLL102-10SC

功能描述

Low Skew Output Buffer

文件大小

180.37 Kbytes

頁面數量

6

生產廠商 PhaseLink Corporation
企業(yè)簡稱

PLL

中文名稱

PhaseLink Corporation官網

原廠標識
數據手冊

下載地址一下載地址二

更新時間

2025-1-22 23:00:00

PLL102-10SC規(guī)格書詳情

DESCRIPTION

The PLL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC or MSOP package. It has two outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than ±350 ps, the device acts as a zero delay buffer.

FEATURES

? Frequency range 50 ~ 120MHz.

? Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to outputs.

? Zero input - output delay.

? Less than 700 ps device - device skew.

? Less than 250 ps skew between outputs.

? Less than 100 ps cycle - cycle jitter.

? 2.5V or 3.3V power supply operation.

? Available in 8-Pin SOIC or MSOP package.

產品屬性

  • 型號:

    PLL102-10SC

  • 制造商:

    PLL

  • 制造商全稱:

    PLL

  • 功能描述:

    Low Skew Output Buffer

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