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PLL102-04SCL-R中文資料PLL數(shù)據(jù)手冊PDF規(guī)格書
PLL102-04SCL-R規(guī)格書詳情
DESCRIPTION
The PLL102-04 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than ±350 ps, the device acts as a zero delay buffer.
FEATURES
? Frequency range 50 ~ 120MHz.
? Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to the outputs (up to 100kHz SST modulation).
? Zero input - output delay.
? Less than 700 ps device - device skew.
? Less than 250 ps skew between outputs.
? Less than 200 ps cycle - cycle jitter.
? Output Enable function tri-state outputs.
? 3.3V operation.
? Available in 8-Pin 150mil SOIC.
產(chǎn)品屬性
- 型號：
PLL102-04SCL-R
- 制造商：
PLL
- 制造商全稱：
PLL
- 功能描述：
Low Skew Output Buffer
| 供應(yīng)商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價格 |
|---|---|---|---|---|---|---|---|
PHASELINK |
08+ |
SOP8 |
2500 |
一級代理,專注軍工、汽車、醫(yī)療、工業(yè)、新能源、電力 |
詢價 | ||
Phaseli |
2020+ |
* |
15000 |
百分百原裝正品 真實公司現(xiàn)貨庫存 本公司只做原裝 可 |
詢價 | ||
Phaselink |
589220 |
16余年資質(zhì) 絕對原盒原盤 更多數(shù)量 |
詢價 | ||||
PhaseLink |
24+ |
SOP8S |
3629 |
原裝優(yōu)勢!房間現(xiàn)貨!歡迎來電! |
詢價 | ||
PHASELINK |
23+ |
NA/ |
2500 |
優(yōu)勢代理渠道,原裝正品,可全系列訂貨開增值稅票 |
詢價 | ||
Phaselink |
23+ |
* |
17500 |
原廠原裝正品 |
詢價 | ||
Phaselink |
* |
39000 |
集團化配單-有更多數(shù)量-免費送樣-原包裝正品現(xiàn)貨-正規(guī) |
詢價 | |||
PHASELINK |
22+ |
原廠原封 |
5000 |
全新原裝現(xiàn)貨!自家?guī)齑? |
詢價 | ||
只做原裝 |
24+ |
SOP-8 |
36520 |
一級代理/放心采購 |
詢價 | ||
PHASELIN |
23+ |
SOP |
5000 |
原裝正品,假一罰十 |
詢價 |
