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LH540205中文資料夏普微數(shù)據(jù)手冊PDF規(guī)格書

LH540205
廠商型號

LH540205

功能描述

CMOS 8192 x 9 Asynchronous FIFO

文件大小

136.47 Kbytes

頁面數(shù)量

17

生產(chǎn)廠商 Sharp Microelectronics of the Americas (SMA)
企業(yè)簡稱

SHARP夏普微

中文名稱

美國夏普微電子公司(SMA)官網(wǎng)

原廠標(biāo)識
數(shù)據(jù)手冊

下載地址一下載地址二

更新時間

2025-2-9 10:16:00

LH540205規(guī)格書詳情

Data words are read out from the LH540205’s output port in precisely the same order that they were written in at its input port; that is, according to a First-In, First Out (FIFO) queue discipline. Since the addressing sequence for a FIFO device’s memory is internally predefined, no external addressing information is required for the operation of the LH540205 device.

FEATURES

? Fast Access Times: 20/25/35/50 ns

? Fast-Fall-Through Time Architecture Based on CMOS Dual-Port SRAM Technology

? Input Port and Output Port Have Entirely Independent Timing

? Expandable in Width and Depth

? Full, Half-Full, and Empty Status Flags

? Data Retransmission Capability

? TTL-Compatible I/O

? Pin and Functionally Compatible with Am/IDT7205

? Control Signals Assertive-LOW for Noise Immunity

? Package: 28-Pin, 300-mil PDIP

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