HY57V561620CLT-P中文資料海力士數(shù)據(jù)手冊PDF規(guī)格書

DESCRIPTION

The HY57V561620C is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V561620C is organized as 4banks of 4,194,304x16.

HY57V561620C is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)

FEATURES

? Single 3.3±0.3V power supply

? All device pins are compatible with LVTTL interface

? JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin

pitch

? All inputs and outputs referenced to positive edge of system clock

? Data mask function by UDQM, LDQM

? Internal four banks operation

? Auto refresh and self refresh

? 8192 refresh cycles / 64ms

? Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or Full page for Sequential Burst

- 1, 2, 4 or 8 for Interleave Burst

? Programmable CAS Latency ; 2, 3 Clocks

? Ambient Temperature: -40~85°C