HY57V561620中文資料海力士數(shù)據(jù)手冊PDF規(guī)格書

The HY57V561620T is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V561620 is organized as 4 banks of 4,194,304x16.

The HY57V561620T is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.