DS21554集成電路（IC）的電信規(guī)格書(shū)PDF中文資料

DESCRIPTION

The DS21354/554 Single-Chip Transceiver (SCT) contains all of the necessary functions for connection to E1 lines. The device is an upward compatible version of the DS2153 and DS2154 SCTs. The onboard clock/data recovery circuitry coverts the AMI/HDB3 E1 waveforms to an NRZ serial stream. The DS21354/554 automatically adjusts to E1 22AWG (0.6 mm) twisted–pair cables from 0 to over 2km in length. The device can generate the necessary G.703 waveshapes for both 75 ohm coax and 120 ohm twisted cables.

FEATURES

Complete E1 (CEPT) PCM-30/ISDN-PRI transceiver functionality

Onboard long and short haul line interface for clock/data recovery and waveshaping

32-bit or 128-bit crystal-less jitter attenuator

Frames to FAS, CAS, CCS, and CRC4 formats

Integral HDLC controller with 64-byte buffers configurable for Sa Bits, DS0 or sub DS0 operation

Dual two–frame elastic store slip buffers that can connect to asynchronous backplanes up to 8.192MHz

Interleaving PCM Bus Operation

8–bit parallel control port that can be used directly on either multiplexed or non–multiplexed buses (Intel or Motorola)

Extracts and inserts CAS signaling

Detects and generates remote and AIS alarms

Programmable output clocks for Fractional E1, H0, and H12 applications

Fully independent transmit and receive functionality

Full access to Si and Sa bits aligned with CRC-4 multiframe

Four separate loopback functions for testing functions

Large counters for bipolar and code violations, CRC4 code word errors, FAS word errors, and E bits

IEEE 1149.1 JTAG-Boundary Scan Architecture

Pin compatible with DS2154/52/352/552 SCTs

3.3V (DS21354) or 5V (DS21554) supply;low power CMOS

100-pin LQFP package (14mm X 14mm)