DS21552集成電路（IC）的電信規(guī)格書PDF中文資料

DESCRIPTION

The DS21352/552 T1 single-chip transceiver contains all of the necessary functions for connection to T1 lines whether they are DS1 long haul or DSX–1 short haul. The clock recovery circuitry automatically adjusts to T1 lines from 0 feet to over 6000 feet in length. The device can generate both DSX–1 line build outs as well as CSU line build-outs of -7.5dB, -15dB, and -22.5dB. The onboard jitter attenuator (selectable to either 32 bits or 128 bits) can be placed in either the transmit or receive data paths. The framer locates the frame and multiframe boundaries and monitors the data stream for alarms.

FEATURES

■ Complete DS1/ISDN–PRI/J1 transceiver functionality

■ Long and Short haul LIU

■ Crystal–less jitter attenuator

■ Generates DSX–1 and CSU line build-outs

■ HDLC controller with 64-byte buffers Configurable for FDL or DS0 operation

■ Dual two–frame elastic store slip buffers that can connect to asynchronous backplanes up to 8.192MHz

■ 8.192MHz clock output locked to RCLK

■ Interleaving PCM Bus Operation

■ Per-channel loopback and idle code insertion

■ 8-bit parallel control port muxed or nonmuxed buses (Intel or Motorola)

■ Programmable output clocks for Fractional T1

■ Fully independent transmit and receive functionality

■ Generates/detects in-band loop codes from 1 to 8 bits in length including CSU loop codes

■ IEEE 1149.1 JTAG-Boundary Scan

■ Pin compatible with DS2152/54/354/554 SCTs

■ 100-pin LQFP package (14 mm x 14 mm) 3.3V (DS21352) or 5V (DS21552) supply; low power CMOS