AK8448中文資料旭化成微電子數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

Features

Maximum Processing Speed

In CDS mode and Clamp mode

1ch, 2ch and 3ch mode: 40M samples/sec per channel

4ch and 6ch mode: 20M sample/sec per channel

In DC Direct-coupled mode

1ch, 2ch and 3ch mode: 15M sample/sec per channel

4ch and 6ch mode: 15M sample/sec per channel

? Maximum Input Level: 1.35Vpp (typ.)@CDS mode and DC connection mode

1.19Vpp (typ.)@Clamp mode

? Compatible with both CCD and CIS Signal Polarities

? Simultaneously Sampling 6-Channel CDS circuits ( Correlated Double Sampling )

? Offset DACs: Adjustable Range : ±298.7 mV (typ.), Independent 6-channel 8 Bit DACs

? PGA: Adjustable Gain Range : 0 dB ~ 18.75 dB (typ.)

Independently adjustable 6-channel 8 Bit PGAs.

? Linearity: DNL = -1LSB (min.), +1LSB (max.) with guaranteed no missing code.

? 5 bit Output Bus: Enables to output 10 Bit Data in 5 Bit x 2 cycles

? 4-Wire Serial Interface

? Supply: 3.3V±0.3V

? Power Dissipation: T.B.D(typ.)@6ch mode, at 20M samples/sec per channel

? Package: 64 Pin LQFP, Pin pitch 0.5 mm, Mold size 10 mm x 10 mm