AK8432中文資料旭化成微電子數(shù)據(jù)手冊(cè)PDF規(guī)格書

□ Maximum processing speed

In CDS mode and clamp mode

1CH, 2CH, 3CH mode: 40M sample / sec per channel

4CH, 6CH mode: 20M sample / sec per channel

In DC direct connection mode

1CH, 2CH, 3CH mode: 10M sample / sec per channel

4CH, 6CH mode: 8.3M sample / sec per channel

□ Maximum input signal level: 1.35Vpp (typ.) @ CDS mode, DC direct connection mode

1.29Vpp (typ.) @ Clamp mode

□ Supports both CCD and CIS signal polarities

□ 6CH Simultaneous Sampling CDS Circuit (Correlated Double Sampling)

□ Offset DAC: Range ± 200 mV (typ.), 8bit, 6 channels independent

□ PGA: Gain adjustment range 0dB ~ 18dB (typ.), 8bit, 6 channels independent

□ Linearity: DNL = ?1LSB (min.), +1.5LSB (max.) Guarantee no missing code

□ 5bit output bus: Outputs 10bit data in 5bit x 2 cycles

□ 4-wire serial interface

□ Power supply: 3.3V ± 0.3V

□ Power consumption: 530mW (typ.) @ 6ch mode, 20M sample / sec per channel

□ Package: 64pin LQFP, pin pitch 0.5mm, mold 10mm × 10mm

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