SY87701VZC集成電路（IC）的應用特定時鐘/定時規(guī)格書PDF中文資料

DESCRIPTION

The SY87701V is a complete Clock Recovery and Data Retiming integrated circuit for data rates from 32Mbps up to 1.25Gbps NRZ. The device is ideally suited for SONET/SDH/ATM and Fibre Channel applications and other high-speed data transmission systems.

Clock recovery and data retiming is performed by synchronizing the on-chip VCO directly to the incoming data stream. The VCO center frequency is controlled by the reference clock frequency and the selected divide ratio. On-chip clock generation is performed through the use of a frequency multiplier PLL with a byte rate source as reference.

FEATURES

■ 3.3V and 5V power supply options

■ Clock and data recovery from 32Mbps up to 1.25Gbps NRZ data stream, clock generation from 32Mbps to 1.25Gbps

■ Complies with Bellcore, ITU/CCITT and ANSI specifications for applications such as OC-1, OC-3, OC-12, ATM, FDDI, Fibre Channel and Gigabit Ethernet, as well as proprietary applications

■ Two on-chip PLLs: one for clock generation and another for clock recovery

■ Selectable reference frequencies

■ Differential PECL high-speed serial I/O

■ Line receiver input: no external buffering needed

■ Link fault indication

■ 100K ECL compatible I/O

■ Available in 32-pin EPAD-TQFP and 28-pin SOIC packages (28-pin SOIC is available, but not recommended for new designs, see page 2 for details

APPLICATIONS

■ SONET/SDH/ATM OC-1, OC-3, OC-12, OC-24

■ Fibre Channel, Escon, SMPTE 259

■ Gigabit Ethernet/Fast Ethernet

■ Proprietary architecture up to 1.25Gbps