STM32MP153C

ST STM32MP15x, DDR3L, STPMIC1A,4KB EEPROM, Oscillator and passive components integrated into a single package

Features ?STSTM32MP15x,DDR3L,STPMIC1A,4KBEEPROM,Oscillatorandpassivecomponentsintegratedintoasinglepackage ?STM32MP15xFeatures: oArm?Cortex?-A7upto800MHzx2 oArm?Cortex?-M4upto209MHz oNEON?SIMDCoprocessorx2 oArm?TrustZone? oUSB2.0HS+PHYx2 oEthernet10

STM32MP153C

具有Arm Dual Cortex-A7 650 Mhz、Arm Cortex-M4實(shí)時協(xié)處理器、TFT顯示器、FD-CAN、安全啟動與加密的MPU; ? 內(nèi)核 \n ?32-bit dual-core Arm? Cortex?-A7? L1 32-Kbyte I / 32-Kbyte D for each core\n? 256-Kbyte unified level 2 cache\n? Arm? NEON? and Arm? TrustZone? \n \n ?32-bit Arm? Cortex?-M4 with FPU/MPU? Up to 209 MHz (Up to 703 CoreMark?)\n \n? Memories \n ?External DDR memory up to 1 Gbyte? up to LPDDR2/LPDDR3-1066 16/32-bit\n? up to DDR3/DDR3L-1066 16/32-bit\n \n ?708 Kbytes of internal SRAM: 256 Kbytes of AXI SYSRAM + 384 Kbytes of AHB SRAM + 64 Kbytes of AHB SRAM in Backup domain and 4 Kbytes of SRAM in Backup domain \n ?Dual mode Quad-SPI memory interface \n ?Flexible external memory controller with up to 16-bit data bus: parallel interface to connect external ICs and SLC NAND memories with up to 8-bit ECC \n? Security/safety \n ?Secure boot, TrustZone? peripherals, active tamper \n ?Cortex?-M4 resources isolation \n? Reset and power management \n ?1.71 V to 3.6 V I/Os supply (5 V-tolerant I/Os) \n ?POR, PDR, PVD and BOR \n ?On-chip LDOs (RETRAM, BKPSRAM, USB 1.8 V, 1.1 V) \n ?Backup regulator (~0.9 V) \n ?Internal temperature sensors \n ?Low-power modes: Sleep, Stop and Standby \n ?DDR memory retention in Standby mode \n ?Controls for PMIC companion chip \n? Low-power consumption \n ?Total current consumption down to 2 μA (Standby mode, no RTC, no LSE, no BKPSRAM, no RETRAM) \n? Clock management \n ?Internal oscillators: 64 MHz HSI oscillator, 4 MHz CSI oscillator, 32 kHz LSI oscillator \n ?External oscillators: 8-48 MHz HSE oscillator, 32.768 kHz LSE oscillator \n ?5 × PLLs with fractional mode \n? General-purpose input/outputs \n ?Up to 176 I/O ports with interrupt capability? Up to 8 secure I/Os\n? Up to 6 Wakeup, 3 tampers, 1 active tamper\n \n? Interconnect matrix \n ?2 bus matrices? 64-bit Arm? AMBA? AXI interconnect, up to 266 MHz\n? 32-bit Arm? AMBA? AHB interconnect, up to 209 MHz\n \n? 3 DMA controllers to unload the CPU \n ?48 physical channels in total \n ?1 × high-speed general-purpose master direct memory access controller (MDMA) \n ?2 × dual-port DMAs with FIFO and request router capabilities for optimal peripheral management? Up to 37 communication peripherals \n ?6 × I2C FM+ (1 Mbit/s, SMBus/PMBus) \n ?4 × UART + 4 × USART (12.5 Mbit/s, ISO7816 interface, LIN, IrDA, SPI slave) \n ?6 × SPI (50 Mbit/s, including 3 with full duplex I2S audio class accuracy via internal audio PLL or external clock) \n ?4 × SAI (stereo audio: I2S, PDM, SPDIF Tx) \n ?SPDIF Rx with 4 inputs \n ?HDMI-CEC interface \n ?MDIO Slave interface \n ?3 × SDMMC up to 8-bit (SD / e?MMC?/ SDIO) \n ?2 × CAN controllers supporting CAN FD protocol, out of which one supports time-triggered CAN (TTCAN) \n ?2 × USB 2.0 high-speed Host+ 1 × USB 2.0 full-speed OTG simultaneously? or 1 × USB 2.0 high-speed Host+ 1 × USB 2.0 high-speed OTG simultaneously\n \n ?10/100M or Gigabit Ethernet GMAC? IEEE 1588v2 hardware, MII/RMII/GMII/RGMII\n \n ?8- to 14-bit camera interface up to 140 Mbyte/s \n? 6 analog peripherals \n ?2 × ADCs with 16-bit max. resolution (12 bits up to 4.5 Msps, 14 bits up to 4 Msps, 16 bits up to 3.6 Msps) \n ?1 × temperature sensor \n ?2 × 12-bit D/A converters (1 MHz) \n ?1 × digital filters for sigma delta modulator (DFSDM) with 8 channels/6 filters \n ?Internal or external ADC/DAC reference VREF+ \n? Graphics \n ?LCD-TFT controller, up to 24-bit // RGB888? up to WXGA (1366 × 768) @60 fps or up to Full HD (1920 × 1080) @30 fps\n? Pixel clock up to 90 MHz\n? Two layers with programmable colour LUT\n \n? Up to 29 timers and 3 watchdogs \n ?2 × 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input \n ?2 × 16-bit advanced motor control timers \n ?10 × 16-bit general-purpose timers (including 2 basic timers without PWM) \n ?5 × 16-bit low-power timers \n ?RTC with sub-second accuracy and hardware calendar \n ?2 × 4 Cortex?-A7 system timers (secure, non-secure, virtual, hypervisor) \n ?1 × SysTick M4 timer \n ?3 × watchdogs (2 × independent and window) \n? Hardware acceleration \n ?AES 128, 192, 256, TDES \n ?HASH (MD5, SHA-1, SHA224, SHA256), HMAC \n ?2 × true random number generator (3 oscillators each) \n ?2 × CRC calculation unit \n? Debug mode \n ?Arm? CoreSight? trace and debug: SWD and JTAG interfaces \n ?8-Kbyte embedded trace buffer \n? 3072-bit fuses including 96-bit unique ID, up to 1184-bit available for user \n? All packages are ECOPACK2 compliant;

The STM32MP153C/F devices are based on the high-performance dual-core Arm? Cortex?-A7 32-bit RISC core operating at up to 800 MHz. The Cortex-A7 processor includes a 32-Kbyte L1 instruction cache for each CPU, a 32-Kbyte L1 data cache for each CPU and a 256-Kbyte level2 cache. The Cortex-A7 processor is a very energy-efficient application processor designed to provide rich performance in high-end wearables, and other low-power embedded and consumer applications. It provides up to 20% more single thread performance than the Cortex-A5 and provides similar performance than the Cortex-A9.\n\n The Cortex-A7 incorporates all features of the high-performance Cortex-A15 and Cortex-A17 processors, including virtualization support in hardware, NEON?, and 128-bit AMBA?4 AXI bus interface.\n\n The STM32MP153C/F devices also embed a Cortex? -M4 32-bit RISC core operating at up to 209 MHz frequency. Cortex-M4 core features a floating point unit (FPU) single precision which supports Arm? single-precision data-processing instructions and data types. The Cortex? -M4 supports a full set of DSP instructions and a memory protection unit (MPU) which enhances application security.\n\n The STM32MP153C/F devices provide an external SDRAM interface supporting external memories up to 8-Gbit density (1 Gbyte), 16 or 32-bit LPDDR2/LPDDR3 or DDR3/DDR3L up to 533 MHz.\n\n The STM32MP153C/F devices incorporate high-speed embedded memories with 708 Kbytes of Internal SRAM (including 256 Kbytes of AXI SYSRAM, 3 banks of 128 Kbytes each of AHB SRAM, 64 Kbytes of AHB SRAM in backup domain and 4 Kbytes of SRAM in backup domain), as well as an extensive range of enhanced I/Os and peripherals connected to APB buses, AHB buses, a 32-bit multi-AHB bus matrix and a 64-bit multi layer AXI interconnect supporting internal and external memories access.\n\n All the devices offer two ADCs, two DACs, a low-power RTC, 12 general-purpose 16-bit timers, two PWM timers for motor control, five low-power timers, a true random number generator (RNG), and a cryptographic acceleration cell. The devices support six digital filters for external sigma delta modulators (DFSDM). They also feature standard and advanced communication interfaces.\n\n

STM32MP153C

Arm? dual Cortex?-A7 800 MHz Cortex?-M4 MPU, TFT, 37 comm. interfaces, 29 timers, adv. analog, crypto

STM32MP153D

STSTM32MP15x,DDR3L,STPMIC1A,4KBEEPROM,Oscillatorandpassivecomponentsintegratedintoasinglepackage

Features ?STSTM32MP15x,DDR3L,STPMIC1A,4KBEEPROM,Oscillatorandpassivecomponentsintegratedintoasinglepackage ?STM32MP15xFeatures: oArm?Cortex?-A7upto800MHzx2 oArm?Cortex?-M4upto209MHz oNEON?SIMDCoprocessorx2 oArm?TrustZone? oUSB2.0HS+PHYx2 oEthernet10

STM32MP153D

Arm?dualCortex?-A7800MHzCortex?-M4MPU,TFT,37comm.interfaces,29timers,adv.analog

STM32MP153D

Arm?dualCortex?-A7800MHzCortex?-M4MPU,TFT,37comm.interfaces,29timers,adv.analog

STM32MP153F

STSTM32MP15x,DDR3L,STPMIC1A,4KBEEPROM,Oscillatorandpassivecomponentsintegratedintoasinglepackage

Features ?STSTM32MP15x,DDR3L,STPMIC1A,4KBEEPROM,Oscillatorandpassivecomponentsintegratedintoasinglepackage ?STM32MP15xFeatures: oArm?Cortex?-A7upto800MHzx2 oArm?Cortex?-M4upto209MHz oNEON?SIMDCoprocessorx2 oArm?TrustZone? oUSB2.0HS+PHYx2 oEthernet10

STM32MP153F

Arm?dualCortex?-A7800MHzCortex?-M4MPU,TFT,37comm.interfaces,29timers,adv.analog,crypto