STM32L4Q5AG

Ultra-low-power with FPU Arm Cortex-M4 MCU 120 MHz with 1024 kbytes of Flash memory, USB OTG, DFSDM, CHROM-ART, AES, PKA; ? Includes ST state-of-the-art patented technology \n? Ultra-low-power with FlexPowerControl \n ?1.71 V to 3.6 V power supply \n ?-40 °C to 85/125 °C temperature range \n ?Batch acquisition mode (BAM) \n ?150 nA in VBAT mode: supply for RTC and 32x32-bit backup registers \n ?22 nA Shutdown mode (5 wakeup pins) \n ?42 nA Standby mode (5 wakeup pins) \n ?190 nA Standby mode with RTC \n ?2.95 μA Stop 2 with RTC \n ?110 μA/MHz Run mode (LDO mode) \n ?41 μA/MHz Run mode (@ 3.3 V SMPS mode) \n ?5 μs wakeup from Stop mode \n ?Brownout reset (BOR) in all modes except Shutdown \n? 內(nèi)核 \n ?Arm? 32-bit Cortex?-M4 CPU with FPU, adaptive real-time accelerator (ART Accelerator) allowing 0-wait-state execution from Flash memory, frequency up to 120 MHz, MPU, 150 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions \n? Memories \n ?1-Mbyte Flash memory, 2 banks read-while-write, proprietary code readout protection \n ?320 Kbytes of SRAM including 64 Kbytes with hardware parity check \n ?External memory interface for static memories supporting SRAM, PSRAM, NOR, NAND and FRAM memories \n ?2 x Octo-SPI memory interfaces \n? General-purpose inputs/outputs \n ?Up to 136 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V \n? Performance benchmark \n ?1.25 DMIPS/MHz (Drystone 2.1) \n ?409.20 CoreMark? (3.41 CoreMark/MHz @120 MHz) \n? Energy benchmark \n ?285 ULPMark?CP score \n? Up to 24 capacitive sensing channels \n ?Support touchkey, linear and rotary touch sensors \n? Clock management \n ?4 to 48 MHz crystal oscillator \n ?32 kHz crystal oscillator for RTC (LSE) \n ?Internal 16 MHz factory-trimmed RC (±1%) \n ?Internal low-power 32 kHz RC (±5%) \n ?Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by LSE (better than ±0.25 % accuracy) \n ?Internal 48 MHz with clock recovery \n ?3 PLLs for system clock, USB, audio, ADC \n? Interconnect matrix \n ?1 AHB bus matrix \n? 14-channel DMA controller? 23 communication peripherals \n ?USB OTG 2.0 full-speed, LPM and BCD \n ?2x SAIs (serial audio interface) \n ?4x I2C FM+(1 Mbit/s), SMBus/PMBus \n ?6x USARTs (ISO 7816, LIN, IrDA, modem) \n ?3x SPIs (5x SPIs with the dual Octo-SPI) \n ?CAN (2.0B Active) and 2x SDMMC \n ?8- to 14-bit camera interface up to 32 MHz (black and white) or 10 MHz (color) \n ?8-/16-bit parallel synchronous data input/output slave interface (PSSI) \n? 11 analog peripherals (independent supply) \n ?2x 12-bit ADC 5 Msps, up to 16-bit with hardware oversampling, 200 μA/Msps \n ?2x 12-bit DAC, low-power sample and hold \n ?2x operational amplifiers with built-in PGA \n ?2x ultra-low-power comparators \n ?2x digital filters for sigma delta modulator \n ?1x temperature sensor \n? Advanced graphics features \n ?Chrom-ART Accelerator (DMA2D) for enhanced graphic content creation \n ?LCD-TFT controller \n? 16x timers and watchdog \n ?2 x 16-bit advanced motor-control \n ?2 x 32-bit general purpose timers \n ?5 x 16-bit general purpose timers \n ?2x 16-bit basic timers \n ?2x low-power 16-bit timers (available in Stop mode) \n ?2x watchdogs \n ?1x SysTick timer \n ?RTC with hardware calendar, alarms and calibration \n? Cryptographic acceleration \n ?AES (128/256-bit key) \n ?Public key accelerator (PKA) \n? True random generator \n? CRC calculation unit \n? HASH (SHA-256) hardware accelerator \n? Debug mode \n ?Serial wire debug (SWD) \n ?JTAG \n ?Embedded Trace Macrocell? (ETM) \n? 96-bit unique ID;

STM32L4Q5xx designates a family of ultra-low-power microcontroller devices (part of STM32L4+ Series) based on the high-performance Arm? Cortex?-M4 32-bit RISC core. They operate at a frequency of up to 120 MHz. \n\n The Cortex-M4 core features a single-precision floating-point unit (FPU), which supports all the Arm? single-precision data-processing instructions and all the data types. The Cortex-M4 core also implements a full set of DSP (digital signal processing) instructions and a memory protection unit (MPU) that enhances the application’s security.\n\n These devices embed high-speed memories (1 Mbyte of Flash memory and 320 Kbytes of SRAM), a flexible external memory controller (FSMC) for static memories (for devices with packages of 100 pins and more), two OCTOSPI Flash memory interfaces (for devices with packages of 100 pins or more) and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix.\n\n These devices embed several protection mechanisms for embedded Flash memory and SRAM: readout protection, write protection, proprietary code readout protection and a firewall.\n\n These devices offer two fast 12-bit ADCs (5 Msps), two comparators, two operational amplifiers, two DAC channels, an internal voltage reference buffer, a low-power RTC, two general-purpose 32-bit timers, two 16-bit PWM timers dedicated to motor control, seven general-purpose 16-bit timers, and two 16-bit low-power timers. The devices support two digital filters for external sigma delta modulators (DFSDMs). In addition, up to 24 capacitive sensing channels are available. \n\n They also feature standard and advanced communication interfaces such as:\n\n - Four I2Cs\n\n - Three SPIs\n\n - Three USARTs, two UARTs and one low-power UART\n\n - Two SAIs \n\n - Two SDMMCs\n\n - One CAN\n\n - One USB OTG full-speed\n\n - Camera interface\n\n - Synchronous parallel data interface (PSSI)\n\n STM32L4Q5xx devices embed an AES and a PKA hardware accelerator.\n\n The devices operate in the -40 to +85 °C (+105 °C junction) and -40 to +125 °C (+130 °C junction) temperature ranges from a 1.71 to 3.6 V power supply. A comprehensive set of power-saving modes allows the design of low-power applications.\n\n Some independent power supplies are supported such as an analog independent supply input for ADC, DAC, OPAMPs and comparators, a 3.3 V dedicated supply input for USB and up to 14 I/Os, which can be supplied independently down to 1.08 V. A VBAT input allows backup of the RTC and the registers. Dedicated VDD12 power supplies can be used to bypass the internal LDO regulator when connected to an external SMPS.\n\n The STM32L4Q5xx family offers eight packages from 48-pin to 169-pin.\n\n

STM32L4Q5AG

Ultra-low-power Arm?Cortex?-M4 32-bit MCUFPU, 150 DMIPS, 1-MB Flash memory, 320-KB SRAM, LCD-TFT, AESPKA

STM32L4Q5CG

Ultra-low-powerArm?Cortex?-M432-bitMCUFPU,150DMIPS,1-MBFlashmemory,320-KBSRAM,LCD-TFT,AESPKA

STM32L4Q5QG

Ultra-low-powerArm?Cortex?-M432-bitMCUFPU,150DMIPS,1-MBFlashmemory,320-KBSRAM,LCD-TFT,AESPKA

STM32L4Q5RG

Ultra-low-powerArm?Cortex?-M432-bitMCUFPU,150DMIPS,1-MBFlashmemory,320-KBSRAM,LCD-TFT,AESPKA

STM32L4Q5VG

Ultra-low-powerArm?Cortex?-M432-bitMCUFPU,150DMIPS,1-MBFlashmemory,320-KBSRAM,LCD-TFT,AESPKA

STM32L4Q5XX

Ultra-low-powerArm?Cortex?-M432-bitMCUFPU,150DMIPS,1-MBFlashmemory,320-KBSRAM,LCD-TFT,AESPKA

STM32L4Q5ZG

Ultra-low-powerArm?Cortex?-M432-bitMCUFPU,150DMIPS,1-MBFlashmemory,320-KBSRAM,LCD-TFT,AESPKA