STM32H7B3ZI

32-bit Arm? Cortex?-M7 280 MHz MCUs, 2-Mbyte flash memory, 1.4-Mbyte RAM, 46 com. and analog interfaces, SMPS, crypto

Features IncludesSTstate-of-the-artpatentedtechnology Core ?32-bitArm?Cortex?-M7corewithdouble-precisionFPUandL1cache: 16Kbytesofdataand16Kbytesofinstructioncacheallowingtofillonecache lineinasingleaccessfromthe128-bitembeddedflashmemory;frequencyup to

STM32H7B3ZI

High-performance and DSP with DP-FPU, Arm Cortex-M7 MCU with 2MBytes of Flash memory, 1376 KB SRAM, 280 MHz CPU, L1 cache, graphic accelerations, external memory interfaces and large set of peripherals; ? Includes ST state-of-the-art patented technology \n? 內(nèi)核 \n ?32-bit Arm? Cortex?-M7 core with double-precision FPU and L1 cache: 16 Kbytes of data and 16 Kbytes of instruction cache allowing to fill one cache line in a single access from the 128-bit embedded flash memory; frequency up to 280 MHz, MPU, 599 DMIPS/ 2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions \n? Memories \n ?2 Mbytes of flash memory with read while write support, plus 1 Kbyte of OTP \n ?~1.4 Mbytes of RAM: 192 Kbytes of TCM RAM (inc. 64 Kbytes of ITCM RAM + 128 Kbytes of DTCM RAM for time critical routines), 1.18 Mbytes of user SRAM, and 4 Kbytes of SRAM in Backup domain \n ?2x Octo-SPI memory interfaces with on-the-fly decryption, I/O multiplexing and support for serial PSRAM/NOR, Hyper RAM/flash frame formats, running up to 140 MHz in SRD mode and up to 110 MHz in DTR mode \n ?Flexible external memory controller with up to 32-bit data bus:? SRAM, PSRAM, NOR flash memory clocked up to 125 MHz in Synchronous mode\n? SDRAM/LPSDR SDRAM,\n? 8/16-bit NAND flash memory\n \n ?CRC calculation unit \n? 安保 \n ?ROP, PC-ROP, active tamper, secure firmware upgrade support, Secure access mode \n? General-purpose input/outputs \n ?Up to 168 I/O ports with interrupt capability? Fast I/Os capable of up to 133 MHz\n? Up to 164 5 V-tolerant I/Os\n \n? Low-power consumption \n ?Stop: down to 32 μA with full RAM retention \n ?Standby: 2.8 μA (Backup SRAM OFF, RTC/LSE ON, PDR OFF) \n ?VBAT: 0.8 μA with RTC and LSE ON \n? Clock management \n ?Internal oscillators: 64 MHz HSI, 48 MHz RC, 4 MHz CSI, 32 kHz LSI \n ?External oscillators: 4-50 MHz HSE, 32.768 kHz LSE \n ?3× PLLs (1 for the system clock, 2 for kernel clocks) with fractional mode \n? Reset and power management \n ?2 separate power domains, which can be independently clock gated to maximize power efficiency:? CPU domain (CD) for Arm? Cortex? core and its peripherals , which can be independently switched in Retention mode\n? mart run domain (SRD) for reset and clock control, power management and some peripherals \n \n ?1.62 to 3.6 V application supply and I/Os \n ?POR, PDR, PVD and BOR \n ?Dedicated USB power embedding a 3.3 V internal regulator to supply the internal PHYs \n ?Dedicated MMC power supply \n ?High power efficiency SMPS step-down converter regulator to directly supply VCORE or an external circuitry \n ?Embedded regulator (LDO) with configurable scalable output to supply the digital circuitry \n ?Voltage scaling in Run and Stop mode \n ?Backup regulator (~0.9 V) \n ?Low-power modes: Sleep, Stop and Standby \n ?VBAT battery operating mode with charging capability \n ?CPU and domain power state monitoring pins \n? Interconnect matrix? 5 DMA controllers to unload the CPU \n ?1× high-speed general-purpose master direct memory access controller (MDMA) \n ?2× dual-port DMAs with FIFO and request router capabilities \n ?1× basic DMA with request router capabilities \n ?1x basic DMA dedicated to DFSDM \n? Up to 35 communication peripherals \n ?4× I2C FM+ interfaces (SMBus/PMBus) \n ?5× USART/5x UARTs (ISO7816 interface, LIN, IrDA, modem control) and 1x LPUART \n ?6× SPIs, including 4 with muxed full-duplex I2S audio class accuracy via internal audio PLL or external clock and 1 x SPI/I2S in LP domain (up to 125 MHz) \n ?2x SAIs (serial audio interface) \n ?SPDIFRX interface \n ?SWPMI single-wire protocol master I/F \n ?MDIO Slave interface \n ?2× SD/SDIO/MMC interfaces (up to 133 MHz) \n ?2× CAN controllers: 2 with CAN FD, 1 with time-triggered CAN (TT-CAN) \n ?1× USB OTG interfaces (1HS/FS) \n ?HDMI-CEC \n ?8- to 14-bit camera interface up to 80 MHz \n ?8-/16-bit parallel synchronous data input/output slave interface (PSSI) \n? 11 analog peripherals \n ?2× ADCs with 16-bit max. resolution (up to 24 channels, up to 3.6 MSPS) \n ?1× analog and 1x digital temperature sensors \n ?1× 12-bit single-channel DAC (in SRD domain) + 1× 12-bit dual-channel DAC \n ?2× ultra-low-power comparators \n ?2× operational amplifiers (8 MHz bandwidth) \n ?2× digital filters for sigma delta modulator (DFSDM), 1x with 8 channels/8 filters and 1x in SRD domain with 2 channels/1 filter \n? Graphics \n ?LCD-TFT controller up to XGA resolution \n ?Chrom-ART graphical hardware Accelerator (DMA2D) to reduce CPU load \n ?Hardware JPEG Codec \n ?Chrom-GRC? (GFXMMU) \n? Up to 19 timers and 2 watchdogs \n ?2× 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input (up to 280 MHz) \n ?2× 16-bit advanced motor control timers (up to 280 MHz) \n ?10× 16-bit general-purpose timers (up to 280 MHz) \n ?3× 16-bit low-power timers (up to 280 MHz) \n ?2× watchdogs (independent and window) \n ?1× SysTick timer \n ?RTC with sub-second accuracy and hardware calendar \n? Cryptographic acceleration \n ?AES chaining modes: ECB,CBC,CTR,GCM,CCM for 128, 192 or 256 \n ?HASH (MD5, SHA-1, SHA-2), HMAC \n ?2x OTFDEC AES-128 in CTR mode for Octo-SPI memory encryption/decryption \n ?1x 32-bit, NIST SP 800-90B compliant , true random generator \n? Debug mode \n ?SWD & JTAG interfaces \n ?4 Kbytes Embedded Trace Buffer \n? 96-bit unique ID;

STM32H7B3xI devices are based on the high-performance Arm? Cortex?-M7 32-bit RISC core operating at up to 280 MHz. The Cortex? -M7 core features a floating point unit (FPU) which supports Arm? double-precision (IEEE 754 compliant) and single-precision data-processing instructions and data types. STM32H7B3xI devices support a full set of DSP instructions and a memory protection unit (MPU) to enhance application security.\n\n STM32H7B3xI devices incorporate high-speed embedded memories with a dual-bank flash memory of 2 Mbytes, around 1.4 Mbyte of RAM (including 192 Kbytes of TCM RAM, 1.18 Mbytes of user SRAM and 4 Kbytes of backup SRAM), as well as an extensive range of enhanced I/Os and peripherals connected to four APB buses, three AHB buses, a 32-bit multi-AHB bus matrix and a multi layer AXI interconnect supporting internal and external memory access.\n\n All the devices offer two ADCs, two DACs (one dual and one single DAC), two ultra-low power comparators, a low-power RTC, 12 general-purpose 16-bit timers, two PWM timers for motor control, three low-power timers, a true random number generator (RNG), and a cryptographic acceleration cell and a HASH processor. The devices support nine digital filters for external sigma delta modulators (DFSDM). They also feature standard and advanced communication interfaces. \n\n

STM32H7B3ZII6QTR

32-bit Arm? Cortex?-M7 280 MHz MCUs, 2-Mbyte flash memory, 1.4-Mbyte RAM, 46 com. and analog interfaces, SMPS, crypto

Features IncludesSTstate-of-the-artpatentedtechnology Core ?32-bitArm?Cortex?-M7corewithdouble-precisionFPUandL1cache: 16Kbytesofdataand16Kbytesofinstructioncacheallowingtofillonecache lineinasingleaccessfromthe128-bitembeddedflashmemory;frequencyup to

STM32H7B3ZII6TR

32-bit Arm? Cortex?-M7 280 MHz MCUs, 2-Mbyte flash memory, 1.4-Mbyte RAM, 46 com. and analog interfaces, SMPS, crypto

Features IncludesSTstate-of-the-artpatentedtechnology Core ?32-bitArm?Cortex?-M7corewithdouble-precisionFPUandL1cache: 16Kbytesofdataand16Kbytesofinstructioncacheallowingtofillonecache lineinasingleaccessfromthe128-bitembeddedflashmemory;frequencyup to

STM32H7B3ZIK6QTR

32-bit Arm? Cortex?-M7 280 MHz MCUs, 2-Mbyte flash memory, 1.4-Mbyte RAM, 46 com. and analog interfaces, SMPS, crypto

Features IncludesSTstate-of-the-artpatentedtechnology Core ?32-bitArm?Cortex?-M7corewithdouble-precisionFPUandL1cache: 16Kbytesofdataand16Kbytesofinstructioncacheallowingtofillonecache lineinasingleaccessfromthe128-bitembeddedflashmemory;frequencyup to

STM32H7B3ZIK6TR

32-bit Arm? Cortex?-M7 280 MHz MCUs, 2-Mbyte flash memory, 1.4-Mbyte RAM, 46 com. and analog interfaces, SMPS, crypto

Features IncludesSTstate-of-the-artpatentedtechnology Core ?32-bitArm?Cortex?-M7corewithdouble-precisionFPUandL1cache: 16Kbytesofdataand16Kbytesofinstructioncacheallowingtofillonecache lineinasingleaccessfromthe128-bitembeddedflashmemory;frequencyup to

STM32H7B3ZIT6QTR

32-bit Arm? Cortex?-M7 280 MHz MCUs, 2-Mbyte flash memory, 1.4-Mbyte RAM, 46 com. and analog interfaces, SMPS, crypto

Features IncludesSTstate-of-the-artpatentedtechnology Core ?32-bitArm?Cortex?-M7corewithdouble-precisionFPUandL1cache: 16Kbytesofdataand16Kbytesofinstructioncacheallowingtofillonecache lineinasingleaccessfromthe128-bitembeddedflashmemory;frequencyup to

STM32H7B3ZIT6TR

32-bit Arm? Cortex?-M7 280 MHz MCUs, 2-Mbyte flash memory, 1.4-Mbyte RAM, 46 com. and analog interfaces, SMPS, crypto

Features IncludesSTstate-of-the-artpatentedtechnology Core ?32-bitArm?Cortex?-M7corewithdouble-precisionFPUandL1cache: 16Kbytesofdataand16Kbytesofinstructioncacheallowingtofillonecache lineinasingleaccessfromthe128-bitembeddedflashmemory;frequencyup to