STM32H750

High-performance value lines

STM32H750

STM32 development boards

STM32H750VB

帶DSP和DP-FPU的高性能ARM Cortex-M7 MCU，具有128 KB Flash、1 MB RAM、480 MHz CPU、一級緩存、外部存儲器接口、JPEG編解碼器、硬件加密和大量外設(shè); ? Includes ST state-of-the-art patented technology \n? 內(nèi)核 \n ?32-bit Arm? Cortex?-M7 core with double-precision FPU and L1 cache: 16 Kbytes of data and 16 Kbytes of instruction cache; frequency up to 480 MHz, MPU, 1027 DMIPS/ 2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions \n? Memories \n ?128 Kbytes of flash memory \n ?1 Mbyte of RAM: 192 Kbytes of TCM RAM (inc. 64 Kbytes of ITCM RAM + 128 Kbytes of DTCM RAM for time critical routines), 864 Kbytes of user SRAM, and 4 Kbytes of SRAM in Backup domain \n ?Dual mode Quad-SPI memory interface running up to 133 MHz \n ?Flexible external memory controller with up to 32-bit data bus:? SRAM, PSRAM, NOR flash memory clocked up to 133 MHz in synchronous mode \n? SDRAM/LPSDR SDRAM\n? 8/16-bit NAND flash memories\n \n ?CRC calculation unit \n? 安保 \n ?ROP, PC-ROP, active tamper, secure firmware upgrade support, Secure access mode \n? General-purpose input/outputs \n ?Up to 168 I/O ports with interrupt capability \n? Reset and power management \n ?3 separate power domains which can be independently clock-gated or switched off:? D1: high-performance capabilities\n? D2: communication peripherals and timers\n? D3: reset/clock control/power management\n \n ?1.62 to 3.6 V application supply and I/Os \n ?POR, PDR, PVD and BOR \n ?Dedicated USB power embedding a 3.3 V internal regulator to supply the internal PHYs \n ?Embedded regulator (LDO) with configurable scalable output to supply the digital circuitry \n ?Voltage scaling in Run and Stop mode (6 configurable ranges) \n ?Backup regulator (~0.9 V) \n ?Voltage reference for analog peripheral/VREF+ \n ?Low-power modes: Sleep, Stop, Standby and VBAT supporting battery charging \n? Low-power consumption \n ?VBAT battery operating mode with charging capability \n ?CPU and domain power state monitoring pins \n ?2.95 μA in Standby mode (Backup SRAM OFF, RTC/LSE ON) \n? Clock management \n ?Internal oscillators: 64 MHz HSI, 48 MHz HSI48, 4 MHz CSI, 32 kHz LSI \n ?External oscillators: 4-48 MHz HSE, 32.768 kHz LSE \n ?3× PLLs (1 for the system clock, 2 for kernel clocks) with Fractional mode \n? Interconnect matrix? 4 DMA controllers to unload the CPU \n ?1× high-speed master direct memory access controller (MDMA) with linked list support \n ?2× dual-port DMAs with FIFO \n ?1× basic DMA with request router capabilities \n? Up to 35 communication peripherals \n ?4× I2Cs FM+ interfaces (SMBus/PMBus) \n ?4× USARTs/4x UARTs (ISO7816 interface, LIN, IrDA, up to 12.5 Mbit/s) and 1x LPUART \n ?6× SPIs, 3 with muxed duplex I2S audio class accuracy via internal audio PLL or external clock, 1x I2S in LP domain (up to 150 MHz) \n ?4x SAIs (serial audio interface) \n ?SPDIFRX interface \n ?SWPMI single-wire protocol master I/F \n ?MDIO Slave interface \n ?2× SD/SDIO/MMC interfaces (up to 125 MHz) \n ?2× CAN controllers: 2 with CAN FD, 1 with time-triggered CAN (TT-CAN) \n ?2× USB OTG interfaces (1FS, 1HS/FS) crystal-less solution with LPM and BCD \n ?Ethernet MAC interface with DMA controller \n ?HDMI-CEC \n ?8- to 14-bit camera interface (up to 80 MHz) \n? 11 analog peripherals \n ?3× ADCs with 16-bit max. resolution (up to 36 channels, up to 3.6 MSPS) \n ?1× temperature sensor \n ?2× 12-bit D/A converters (1 MHz) \n ?2× ultra-low-power comparators \n ?2× operational amplifiers (7.3 MHz bandwidth) \n ?1× digital filters for sigma delta modulator (DFSDM) with 8 channels/4 filters \n? Graphics \n ?LCD-TFT controller up to XGA resolution \n ?Chrom-ART graphical hardware Accelerator (DMA2D) to reduce CPU load \n ?Hardware JPEG Codec \n? Up to 22 timers and watchdogs \n ?1× high-resolution timer (2.1 ns max resolution) \n ?2× 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input (up to 240 MHz) \n ?2× 16-bit advanced motor control timers (up to 240 MHz) \n ?10× 16-bit general-purpose timers (up to 240 MHz) \n ?5× 16-bit low-power timers (up to 240 MHz) \n ?2× watchdogs (independent and window) \n ?1× SysTick timer \n ?RTC with sub-second accuracy and hardware calendar \n? Cryptographic acceleration \n ?AES 128, 192, 256, TDES, \n ?HASH (MD5, SHA-1, SHA-2), HMAC \n ?True random number generators \n? Debug mode \n ?SWD & JTAG interfaces \n ?4-Kbyte embedded trace buffer \n? 96-bit unique ID;

STM32H750xB devices are based on the high-performance Arm? Cortex?-M7 32-bit RISC core operating at up to 480 MHz. The Cortex? -M7 core features a floating point unit (FPU) which supports Arm? double-precision (IEEE 754 compliant) and single-precision data-processing instructions and data types. STM32H750xB devices support a full set of DSP instructions and a memory protection unit (MPU) to enhance application security.\n\n STM32H750xB devices incorporate high-speed embedded memories with a flash memory of 128 Kbytes, up to 1 Mbyte of RAM (including 192 Kbytes of TCM RAM, up to 864 Kbytes of user SRAM and 4 Kbytes of backup SRAM), as well as an extensive range of enhanced I/Os and peripherals connected to APB buses, AHB buses, 2x32-bit multi-AHB bus matrix and a multi layer AXI interconnect supporting internal and external memory access.\n\n All the devices offer three ADCs, two DACs, two ultra-low power comparators, a low-power RTC, a high-resolution timer, 12 general-purpose 16-bit timers, two PWM timers for motor control, five low-power timers, a true random number generator (RNG), and a cryptographic acceleration cell. The devices support four digital filters for external sigma-delta modulators (DFSDM). They also feature standard and advanced communication interfaces. \n\n

STM32H750XB

帶DSP和DP-FPU的高性能ARM Cortex-M7 MCU，具有128 KB Flash、1 MB RAM、480 MHz CPU、一級緩存、外部存儲器接口、JPEG編解碼器、硬件加密和大量外設(shè); ? Includes ST state-of-the-art patented technology \n? 內(nèi)核 \n ?32-bit Arm? Cortex?-M7 core with double-precision FPU and L1 cache: 16 Kbytes of data and 16 Kbytes of instruction cache; frequency up to 480 MHz, MPU, 1027 DMIPS/ 2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions \n? Memories \n ?128 Kbytes of flash memory \n ?1 Mbyte of RAM: 192 Kbytes of TCM RAM (inc. 64 Kbytes of ITCM RAM + 128 Kbytes of DTCM RAM for time critical routines), 864 Kbytes of user SRAM, and 4 Kbytes of SRAM in Backup domain \n ?Dual mode Quad-SPI memory interface running up to 133 MHz \n ?Flexible external memory controller with up to 32-bit data bus:? SRAM, PSRAM, NOR flash memory clocked up to 133 MHz in synchronous mode \n? SDRAM/LPSDR SDRAM\n? 8/16-bit NAND flash memories\n \n ?CRC calculation unit \n? 安保 \n ?ROP, PC-ROP, active tamper, secure firmware upgrade support, Secure access mode \n? General-purpose input/outputs \n ?Up to 168 I/O ports with interrupt capability \n? Reset and power management \n ?3 separate power domains which can be independently clock-gated or switched off:? D1: high-performance capabilities\n? D2: communication peripherals and timers\n? D3: reset/clock control/power management\n \n ?1.62 to 3.6 V application supply and I/Os \n ?POR, PDR, PVD and BOR \n ?Dedicated USB power embedding a 3.3 V internal regulator to supply the internal PHYs \n ?Embedded regulator (LDO) with configurable scalable output to supply the digital circuitry \n ?Voltage scaling in Run and Stop mode (6 configurable ranges) \n ?Backup regulator (~0.9 V) \n ?Voltage reference for analog peripheral/VREF+ \n ?Low-power modes: Sleep, Stop, Standby and VBAT supporting battery charging \n? Low-power consumption \n ?VBAT battery operating mode with charging capability \n ?CPU and domain power state monitoring pins \n ?2.95 μA in Standby mode (Backup SRAM OFF, RTC/LSE ON) \n? Clock management \n ?Internal oscillators: 64 MHz HSI, 48 MHz HSI48, 4 MHz CSI, 32 kHz LSI \n ?External oscillators: 4-48 MHz HSE, 32.768 kHz LSE \n ?3× PLLs (1 for the system clock, 2 for kernel clocks) with Fractional mode \n? Interconnect matrix? 4 DMA controllers to unload the CPU \n ?1× high-speed master direct memory access controller (MDMA) with linked list support \n ?2× dual-port DMAs with FIFO \n ?1× basic DMA with request router capabilities \n? Up to 35 communication peripherals \n ?4× I2Cs FM+ interfaces (SMBus/PMBus) \n ?4× USARTs/4x UARTs (ISO7816 interface, LIN, IrDA, up to 12.5 Mbit/s) and 1x LPUART \n ?6× SPIs, 3 with muxed duplex I2S audio class accuracy via internal audio PLL or external clock, 1x I2S in LP domain (up to 150 MHz) \n ?4x SAIs (serial audio interface) \n ?SPDIFRX interface \n ?SWPMI single-wire protocol master I/F \n ?MDIO Slave interface \n ?2× SD/SDIO/MMC interfaces (up to 125 MHz) \n ?2× CAN controllers: 2 with CAN FD, 1 with time-triggered CAN (TT-CAN) \n ?2× USB OTG interfaces (1FS, 1HS/FS) crystal-less solution with LPM and BCD \n ?Ethernet MAC interface with DMA controller \n ?HDMI-CEC \n ?8- to 14-bit camera interface (up to 80 MHz) \n? 11 analog peripherals \n ?3× ADCs with 16-bit max. resolution (up to 36 channels, up to 3.6 MSPS) \n ?1× temperature sensor \n ?2× 12-bit D/A converters (1 MHz) \n ?2× ultra-low-power comparators \n ?2× operational amplifiers (7.3 MHz bandwidth) \n ?1× digital filters for sigma delta modulator (DFSDM) with 8 channels/4 filters \n? Graphics \n ?LCD-TFT controller up to XGA resolution \n ?Chrom-ART graphical hardware Accelerator (DMA2D) to reduce CPU load \n ?Hardware JPEG Codec \n? Up to 22 timers and watchdogs \n ?1× high-resolution timer (2.1 ns max resolution) \n ?2× 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input (up to 240 MHz) \n ?2× 16-bit advanced motor control timers (up to 240 MHz) \n ?10× 16-bit general-purpose timers (up to 240 MHz) \n ?5× 16-bit low-power timers (up to 240 MHz) \n ?2× watchdogs (independent and window) \n ?1× SysTick timer \n ?RTC with sub-second accuracy and hardware calendar \n? Cryptographic acceleration \n ?AES 128, 192, 256, TDES, \n ?HASH (MD5, SHA-1, SHA-2), HMAC \n ?True random number generators \n? Debug mode \n ?SWD & JTAG interfaces \n ?4-Kbyte embedded trace buffer \n? 96-bit unique ID;

STM32H750xB devices are based on the high-performance Arm? Cortex?-M7 32-bit RISC core operating at up to 480 MHz. The Cortex? -M7 core features a floating point unit (FPU) which supports Arm? double-precision (IEEE 754 compliant) and single-precision data-processing instructions and data types. STM32H750xB devices support a full set of DSP instructions and a memory protection unit (MPU) to enhance application security.\n\n STM32H750xB devices incorporate high-speed embedded memories with a flash memory of 128 Kbytes, up to 1 Mbyte of RAM (including 192 Kbytes of TCM RAM, up to 864 Kbytes of user SRAM and 4 Kbytes of backup SRAM), as well as an extensive range of enhanced I/Os and peripherals connected to APB buses, AHB buses, 2x32-bit multi-AHB bus matrix and a multi layer AXI interconnect supporting internal and external memory access.\n\n All the devices offer three ADCs, two DACs, two ultra-low power comparators, a low-power RTC, a high-resolution timer, 12 general-purpose 16-bit timers, two PWM timers for motor control, five low-power timers, a true random number generator (RNG), and a cryptographic acceleration cell. The devices support four digital filters for external sigma-delta modulators (DFSDM). They also feature standard and advanced communication interfaces. \n\n

STM32H750ZB

帶DSP和DP-FPU的高性能ARM Cortex-M7 MCU，具有2 MB Flash、1 MB RAM、480 MHz CPU、ART加速器、一級緩存、外部存儲器接口、包括加密加速器在內(nèi)的大量外設(shè)以及安全服務(wù)支持; ? Includes ST state-of-the-art patented technology \n? 內(nèi)核 \n ?32-bit Arm? Cortex?-M7 core with double-precision FPU and L1 cache: 16 Kbytes of data and 16 Kbytes of instruction cache; frequency up to 480 MHz, MPU, 1027 DMIPS/ 2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions \n? Memories \n ?128 Kbytes of flash memory \n ?1 Mbyte of RAM: 192 Kbytes of TCM RAM (inc. 64 Kbytes of ITCM RAM + 128 Kbytes of DTCM RAM for time critical routines), 864 Kbytes of user SRAM, and 4 Kbytes of SRAM in Backup domain \n ?Dual mode Quad-SPI memory interface running up to 133 MHz \n ?Flexible external memory controller with up to 32-bit data bus:? SRAM, PSRAM, NOR flash memory clocked up to 133 MHz in synchronous mode \n? SDRAM/LPSDR SDRAM\n? 8/16-bit NAND flash memories\n \n ?CRC calculation unit \n? 安保 \n ?ROP, PC-ROP, active tamper, secure firmware upgrade support, Secure access mode \n? General-purpose input/outputs \n ?Up to 168 I/O ports with interrupt capability \n? Reset and power management \n ?3 separate power domains which can be independently clock-gated or switched off:? D1: high-performance capabilities\n? D2: communication peripherals and timers\n? D3: reset/clock control/power management\n \n ?1.62 to 3.6 V application supply and I/Os \n ?POR, PDR, PVD and BOR \n ?Dedicated USB power embedding a 3.3 V internal regulator to supply the internal PHYs \n ?Embedded regulator (LDO) with configurable scalable output to supply the digital circuitry \n ?Voltage scaling in Run and Stop mode (6 configurable ranges) \n ?Backup regulator (~0.9 V) \n ?Voltage reference for analog peripheral/VREF+ \n ?Low-power modes: Sleep, Stop, Standby and VBAT supporting battery charging \n? Low-power consumption \n ?VBAT battery operating mode with charging capability \n ?CPU and domain power state monitoring pins \n ?2.95 μA in Standby mode (Backup SRAM OFF, RTC/LSE ON) \n? Clock management \n ?Internal oscillators: 64 MHz HSI, 48 MHz HSI48, 4 MHz CSI, 32 kHz LSI \n ?External oscillators: 4-48 MHz HSE, 32.768 kHz LSE \n ?3× PLLs (1 for the system clock, 2 for kernel clocks) with Fractional mode \n? Interconnect matrix? 4 DMA controllers to unload the CPU \n ?1× high-speed master direct memory access controller (MDMA) with linked list support \n ?2× dual-port DMAs with FIFO \n ?1× basic DMA with request router capabilities \n? Up to 35 communication peripherals \n ?4× I2Cs FM+ interfaces (SMBus/PMBus) \n ?4× USARTs/4x UARTs (ISO7816 interface, LIN, IrDA, up to 12.5 Mbit/s) and 1x LPUART \n ?6× SPIs, 3 with muxed duplex I2S audio class accuracy via internal audio PLL or external clock, 1x I2S in LP domain (up to 150 MHz) \n ?4x SAIs (serial audio interface) \n ?SPDIFRX interface \n ?SWPMI single-wire protocol master I/F \n ?MDIO Slave interface \n ?2× SD/SDIO/MMC interfaces (up to 125 MHz) \n ?2× CAN controllers: 2 with CAN FD, 1 with time-triggered CAN (TT-CAN) \n ?2× USB OTG interfaces (1FS, 1HS/FS) crystal-less solution with LPM and BCD \n ?Ethernet MAC interface with DMA controller \n ?HDMI-CEC \n ?8- to 14-bit camera interface (up to 80 MHz) \n? 11 analog peripherals \n ?3× ADCs with 16-bit max. resolution (up to 36 channels, up to 3.6 MSPS) \n ?1× temperature sensor \n ?2× 12-bit D/A converters (1 MHz) \n ?2× ultra-low-power comparators \n ?2× operational amplifiers (7.3 MHz bandwidth) \n ?1× digital filters for sigma delta modulator (DFSDM) with 8 channels/4 filters \n? Graphics \n ?LCD-TFT controller up to XGA resolution \n ?Chrom-ART graphical hardware Accelerator (DMA2D) to reduce CPU load \n ?Hardware JPEG Codec \n? Up to 22 timers and watchdogs \n ?1× high-resolution timer (2.1 ns max resolution) \n ?2× 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input (up to 240 MHz) \n ?2× 16-bit advanced motor control timers (up to 240 MHz) \n ?10× 16-bit general-purpose timers (up to 240 MHz) \n ?5× 16-bit low-power timers (up to 240 MHz) \n ?2× watchdogs (independent and window) \n ?1× SysTick timer \n ?RTC with sub-second accuracy and hardware calendar \n? Cryptographic acceleration \n ?AES 128, 192, 256, TDES, \n ?HASH (MD5, SHA-1, SHA-2), HMAC \n ?True random number generators \n? Debug mode \n ?SWD & JTAG interfaces \n ?4-Kbyte embedded trace buffer \n? 96-bit unique ID;

STM32H750xB devices are based on the high-performance Arm? Cortex?-M7 32-bit RISC core operating at up to 480 MHz. The Cortex? -M7 core features a floating point unit (FPU) which supports Arm? double-precision (IEEE 754 compliant) and single-precision data-processing instructions and data types. STM32H750xB devices support a full set of DSP instructions and a memory protection unit (MPU) to enhance application security.\n\n STM32H750xB devices incorporate high-speed embedded memories with a flash memory of 128 Kbytes, up to 1 Mbyte of RAM (including 192 Kbytes of TCM RAM, up to 864 Kbytes of user SRAM and 4 Kbytes of backup SRAM), as well as an extensive range of enhanced I/Os and peripherals connected to APB buses, AHB buses, 2x32-bit multi-AHB bus matrix and a multi layer AXI interconnect supporting internal and external memory access.\n\n All the devices offer three ADCs, two DACs, two ultra-low power comparators, a low-power RTC, a high-resolution timer, 12 general-purpose 16-bit timers, two PWM timers for motor control, five low-power timers, a true random number generator (RNG), and a cryptographic acceleration cell. The devices support four digital filters for external sigma-delta modulators (DFSDM). They also feature standard and advanced communication interfaces. \n\n

STM32H750B-DK

Discovery kits with STM32H745XI and STM32H750XB MCUs

STM32H750B-DK

STM32 development boards

STM32H750IB

32-bit Arm? Cortex?-M7 480MHz MCUs, 128 Kbyte Flash, 1 Mbyte RAM, 46 com. and analog interfaces, crypto

STM32H750IB

32-bit Arm? Cortex?-M7 480MHz MCUs, 128 Kbyte Flash, 1 Mbyte RAM, 46 com. and analog interfaces, crypto

STM32H750IBK6

32-bit Arm? Cortex?-M7 480MHz MCUs, 128 Kbyte Flash, 1 Mbyte RAM, 46 com. and analog interfaces, crypto