STM32F405OEY6TR中文資料意法半導體數(shù)據(jù)手冊PDF規(guī)格書

Features

? Core: Arm? 32-bit Cortex?-M4 CPU with FPU,

Adaptive real-time accelerator (ART

Accelerator) allowing 0-wait state execution

from Flash memory, frequency up to 168 MHz,

memory protection unit, 210 DMIPS/

1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions

? Memories

– Up to 1 Mbyte of Flash memory

– Up to 192+4 Kbytes of SRAM including 64-

Kbyte of CCM (core coupled memory) data

RAM

– 512 bytes of OTP memory

– Flexible static memory controller

supporting Compact Flash, SRAM,

PSRAM, NOR and NAND memories

? LCD parallel interface, 8080/6800 modes

? Clock, reset and supply management

– 1.8 V to 3.6 V application supply and I/Os

– POR, PDR, PVD and BOR

– 4-to-26 MHz crystal oscillator

– Internal 16 MHz factory-trimmed RC (1

accuracy)

– 32 kHz oscillator for RTC with calibration

– Internal 32 kHz RC with calibration

? Low-power operation

– Sleep, Stop and Standby modes

– VBAT supply for RTC, 20×32 bit backup

registers + optional 4 KB backup SRAM

? 3×12-bit, 2.4 MSPS A/D converters: up to 24

channels and 7.2 MSPS in triple interleaved mode

? 2×12-bit D/A converters

? General-purpose DMA: 16-stream DMA

controller with FIFOs and burst support