STLVDS47BDR中文資料意法半導(dǎo)體數(shù)據(jù)手冊(cè)PDF規(guī)格書

DESCRIPTION

The STLVDS47 is a quad CMOS flow-through differential line driver designed for applications requiring ultra low power dissipation and high data rate. The device is designed to support data rates in excess of 400Mbps (200 MHz) utilizing Low Voltage Differential Signaling (LVDS) techology.

The STLVDS47 accepts low voltage TTL/CMOS input levels and translates them to low voltage (350 mV) differential output signals. In addition, the driver support a TRI-STATE function that may be used to disable the output stage, disabling the load current, and thus dropping the device to an ultra low idle power state of 1.3mW typical. The STLVDS47 has a flow-through pinout for easy PCB layout.

The EN and EN* inputs are ANDed together and control the TRI-STATE output.

The STLVDS47 and companion line receiver (STLVDS48) provide a new alternative to high power pseudo-ECL devices for high-speed point-to-point interface applications.

■ >400 MBPS (200MHZ) SWITCHING RATES

■ FLOW-THROUGH PINOUT SIMPLIFIES PCB LAYOUT

■ 300ps (MAX.) DIFFERENTIAL SKEW

■ 1.8 ns (TYP.) PROPAGATION DELAY

■ 3.3V POWER SUPPLY DESIGN

■ ±350 mV DIFFERENTIAL SIGNALING

■ LOW POWER DISSIPATION (3.5mW AT 3.3V STATIC IN TRISTATE)

■ INTEROPERABLE WITH EXISTING 5V LVDS RECEIVERS

■ HIGH IMPEDANCE ON LVDS OUTPUT ON POWER DOWN

■ CONFORMS TO TIA/EIA-644 LVDS STANDARD

■ INDUSTRIAL OPERATING TEMPERATURE RANGE (-40 °C TO +85 °C)

■ AVAILABLE IN SURFACE MOUNT (SOIC) AND LOW PROFILE TSSOP PACKAGE