STE100集成電路（IC）的驅(qū)動(dòng)器接收器收發(fā)器規(guī)格書PDF中文資料

STE100屬于集成電路（IC）的驅(qū)動(dòng)器接收器收發(fā)器。由意法半導(dǎo)體集團(tuán)制造生產(chǎn)的STE100驅(qū)動(dòng)器，接收器，收發(fā)器該系列產(chǎn)品的主要功能是提供必需的硬件資源，以通過延長電纜或印制線進(jìn)行通信。確切的功能會(huì)因所采用的通信協(xié)議而異，可能包括諸如瞬態(tài)抑制之類的功能，這些功能對于通信用途可能并非絕對必要，但對于可能的使用環(huán)境卻是明智之選。

DESCRIPTION

The STE10/100 is a high performance PCI Fast Ethernet controller with integrated physical layer interface for 10BASE-T and 100BASE-TX application.

FEATURES

Industry standard

■ IEEE802.3u 100BASE-TX and IEEE802.3 10BASE-T compliant

■ Support for IEEE802.3x flow control

■ IEEE802.3u Auto-Negotiation support for 10BASE-T and 100BASE-TX

■ PCI bus interface Rev. 2.2 compliant

■ ACPI and PCI power management standard compliant

■ Support PC99 wake on LAN

FIFO

■ Provides independent transmission and receiving FIFOs, each 2k bytes long

■ Pre-fetches up to two transmit packets to minimize inter frame gap (IFG) to 0.96us

■ Retransmits collided packet without reload from host memory within 64 bytes.

■ Automatically retransmits FIFO under-run packet with maximum drain threshold until 3rd time retry failure without influencing the registers and transmit threshold of next packet.

PCI I/F

■ Provides 32-bit PCI bus master data transfer

■ Supports PCI clock with frequency from 0Hz to 33MHz

■ Supports network operation with PCI system clock from 20MHz to 33MHz

■ Provides performance meter and PCI bus master latency timer for tuning the threshold to enhance the performance

■ Provides burst transmit packet interrupt and transmit/receive early interrupt to reduce host CPU utilization

■ As bus master, supports memory-read, memory-read-line, memory-read-multiple, memory-write, memory-write-and-invalidate command

■ Supports big or little endian byte ordering

EEPROM/Boot ROM I/F

■ Provides writeable Flash ROM and EPROM as boot ROM, up to 128kB

■ Provides PCI to access boot ROM by byte, word, or double word

■ Re-writes Flash boot ROM through I/O port by programming register

■ Provides serial interface for read/write 93C46 EEPROM

■ Automatically loads device ID, vendor ID, subsystem ID, subsystem vendor ID, Maximum-Latency , and Minimum-Grand from the 64 byte contents of 93C46 after PCI reset de-asserted

MAC/Physical

■ Integrates the complete set of Physical layer 100BASE-TX and 10BASE-T functions

■ Provides Full-duplex operation in both 100Mbps and 10Mbps modes

■ Provides Auto-negotiation (NWAY) function of full/half duplex operation for both 10 and 100 Mbps

■ Provides MLT-3 transceiver with DC restoration for Base-line wander compensation

■ Provides transmit wave-shaper, receive filters, and adaptive equalizer

■ Provides MAC and Transceiver (TXCVR) loop-back modes for diagnostic

■ Built-in Stream Cipher Scrambler/ De-scrambler and 4B/5B encoder/decoder

■ Supports external transmit transformer with 1.414:1 turn ratio

■ Supports external receive transformer with 1:1 turn ratio

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