SL74HC373中文資料SLS數(shù)據(jù)手冊(cè)PDF規(guī)格書
| 廠商型號(hào) |
SL74HC373 |
| 功能描述 | Octal 3-State Noninverting Transparent Latch |
| 文件大小 |
53.24 Kbytes |
| 頁面數(shù)量 |
5 頁 |
| 生產(chǎn)廠商 | System Logic Semiconductor |
| 企業(yè)簡(jiǎn)稱 |
SLS |
| 中文名稱 | System Logic Semiconductor官網(wǎng) |
| 原廠標(biāo)識(shí) |  |
| 數(shù)據(jù)手冊(cè) | |
| 更新時(shí)間 | 2025-3-11 8:00:00 |
| 人工找貨 | SL74HC373價(jià)格和庫(kù)存，歡迎聯(lián)系客服免費(fèi)人工找貨 |
SL74HC373規(guī)格書詳情
Octal 3-State Noninverting Transparent Latch
High-Performance Silicon-Gate CMOS
The SL74HC373 is identical in pinout to the LS/ALS373. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs.
These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. When Latch Enable goes low, data meeting the setup and hold time becomes latched.
The Output Enable input does not affect the state of the latches, but when Output Enable is high, all device outputs are forced to the high-impedance state. Thus, data may be latched even when the outputs are not enabled.
? Outputs Directly Interface to CMOS, NMOS, and TTL
? Operating Voltage Range: 2.0 to 6.0 V
? Low Input Current: 1.0 μA
? High Noise Immunity Characteristic of CMOS Devices
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|---|---|---|---|---|---|---|---|
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2016+ |
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1500 |
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SLS |
24+ |
SOP |
35200 |
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22+ |
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12000 |
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