SI5325SLASH26-EVB中文資料思佳訊數(shù)據(jù)手冊PDF規(guī)格書

Features

? Generates any frequency from 2 kHz

to 945 MHz and select frequencies to

1.4 GHz from an input frequency of

2 kHz to 710 MHz

? Ultra-low jitter clock outputs with jitter

generation as low as 0.3 ps rms

(50 kHz–80 MHz)

? Integrated loop filter with selectable

loop bandwidth (60 Hz to 8.4 kHz)

? Meets OC-192 GR-253-CORE jitter

specifications

? Dual clock inputs with manual or

automatically controlled hitless

switching (LVPECL, LVDS, CML,

CMOS)

? Dual clock outputs with selectable

signal format

? Support for ITU G.709 and custom

FEC ratios (255/238, 255/237,

255/236)

? LOL, LOS, FOS alarm outputs

? Digitally-controlled output phase

adjustment

? I2C or SPI programmable

? On-chip voltage regulator for

1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%

operation

? Small size: 6 x 6 mm 36-lead QFN

? Pb-free, ROHS compliant