SAF-C165-LM中文資料西門子數(shù)據(jù)手冊(cè)PDF規(guī)格書

C16x-Family of High-Performance CMOS 16-Bit Microcontrollers

Preliminary

C165 16-Bit Microcontroller

● High Performance 16-bit CPU with 4-Stage Pipeline

● 100 ns Instruction Cycle Time at 20-MHz CPU Clock

● 500 ns Multiplication (16 × 16 bits), 1 μs Division (32 / 16 bit)

● Enhanced Boolean Bit Manipulation Facilities

● Additional Instructions to Support HLL and Operating Systems

● Register-Based Design with Multiple Variable Register Banks

● Single-Cycle Context Switching Support

● Up to 16 MBytes Linear Address Space for Code and Data

● 2 KBytes On-Chip RAM

● 4 KBytes On-Chip ROM (RM types only)

● Programmable External Bus Characteristics for Different Address Ranges

● 8-Bit or 16-Bit External Data Bus

● Multiplexed or Demultiplexed External Address/Data Buses

● Five Programmable Chip-Select Signals

● Hold- and Hold-Acknowledge Bus Arbitration Support

● 1024 Bytes On-Chip Special Function Register Area

● Idle and Power Down Modes

● 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event

Controller (PEC)

● 16-Priority-Level Interrupt System with 28 Sources, Sample-Rate down to 50 ns

● Two Multi-Functional General Purpose Timer Units with 5 Timers

● Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous)

● Programmable Watchdog Timer

● Up to 77 General Purpose I/O Lines

● Supported by a Wealth of Development Tools like C-Compilers, Macro-Assembler Packages,

Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers,

Programming Boards

● On-Chip Bootstrap Loader

● 100-Pin MQFP Package (EIAJ)

● 100-Pin TQFP Package (Thin QFP)