S3C24A0中文資料三星數(shù)據(jù)手冊PDF規(guī)格書

ARCHITECTURAL OVERVIEW

The S3C24A0 is a 16/32-bit RISC microprocessor, which is designed to provide a cost-effective, low power, and high performance micro-controller solution for mobile phones and general applications. To provide a sufficient H/W performance for the 2.5G & 3G communication services, the S3C24A0 adopts dual-32-bit bus architecture and includes many powerful hardware accelerators for the motion video processing, serial communications, and etc. For the real time video conferencing, an optimized MPEG4 H/W Encoder/Decoder is integrated. To reduce total system cost and enhance overall functionality, the S3C24A0 also includes following components: separate 16KB Instruction and 16KB Data Cache, MMU to handle virtual memory management, LCD controller (TFT), Camera Interface, MPEG-4 ME, MC, DCTQ, NAND Flash Boot loader, System Manager (power management & etc.), SDRAM controller, 2-ch UART, 4-ch DMA, 4-ch Timers, General I/O Ports, IIC-BUS interface, USB Host, SD Host & Multi-Media Card Interface, Memory Stick Interface, PLL for clock generation & etc. The S3C24A0 can be used as a most powerful Application Processor for mobiles phones. For this application, the S3C24A0 has a Modem Interface to communicate with various Modem Chips.

FEATURES

This section summarizes the features of the S3C24A0. Figure 1-1 is an overall block diagram of the S3C24A0.

Microprocessor and Overall Architecture

? SoC (System-on-Chip) for mobile phones and general embedded applications.

? 16/32-Bit RISC architecture and powerful instruction set with ARM926EJ-S CPU core.

? ARM’s Jazelle Java technology

? Enhanced ARM architecture MMU to support WinCE, Symbian and Linux

? Instruction cache, data cache, write buffer and Physical address TAG RAM to reduce the effect of main memory bandwidth and latency on performance

? 4 way set-associative cache with I-Cache (16KB) and D-Cache (16KB).

? 8-words per line with one valid bit and two dirty bits per line

? Pseudo random or round robin replacement algorithm.

? Write through or write back cache operation to update the main memory.

? The write buffer can hold 16 words of data and four addresses.

? ARM926EJ-S core supports the ARM debug architecture

? Internal AMBA (Advanced Microcontroller Bus Architecture) (AMBA2.0, AHB/APB)

? Dual AHB bus for high-performance processing (AHB-I & AHB-S)