QL2003中文資料etc未分類制造商數(shù)據(jù)手冊PDF規(guī)格書
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QL2003規(guī)格書詳情
[QuickLogic]
PRODUCT SUMMARY
The QL2003 is a 3,000 usable ASIC gate, 5,000 usable PLD gate member of the pASIC 2 family of FPGAs. pASIC 2 FPGAs employ a unique combination of architecture, technology, and software tools to provide high speed, high usable density, low price, and flexibility in the same devices. The flexibility and speed make pASIC 2 devices an efficient and high performance silicon solution for designs described using HDLs such as Verilog and VHDL, as well as schematics.
FEATURES
Ultimate Verilog/VHDL Silicon Solution
- Abundant, high-speed interconnect eliminates manual routing
- Flexible logic cell provides high efficiency and performance
- Design tools produce fast, efficient Verilog/VHDL synthesis
Speed, Density, Low Cost and Flexibility in One Device
- 16-bit counter speeds exceeding 200 MHz
- 3,000 usable ASIC gates, 5,000 usable PLD gates, 118 I/Os
- 3-layer metal ViaLink? process for small die sizes
- 100 routable and pin-out maintainable
Advanced Logic Cell and I/O Capabilities
- Complex functions (up to 16 inputs) in a single logic cell
- High synthesis gate utilization from logic cell fragments
- Full IEEE Standard JTAG boundary scan capability
- Individually-controlled input/feedback registers and OEs on all I/O pins
Other Important Family Features
- 3.3V and 5.0V operation with low standby power
- I/O pin-compatibility between different devices in the same packages
- PCI compliant (at 5.0V), full speed 33 MHz implementations
- High design security provided by security fuses
Total of 118 I/O Pins
- 110 bidirectional input/output pins, PCI-compliant at 5.0V in -1/-2 speed grades
- 4 high-drive input-only pins
- 4 high-drive input/distributed network pins
Four Low-Skew (less than 0.5ns) Distributed Networks
- Two array networks available to logic cell flip-flop clock, set, and reset - each driven by an input-only pin
- Two global clock/control networks available to F1 logic input, and logic cell flip-flop clock, set, reset; input and I/O register clock, reset, enable; and output enable controls - each driven by an input-only pin, or any input or I/O pin, or any logic cell output or I/O cell feedback
High Performance
- Input + logic cell + output delays under 6 ns
- Datapath speeds exceeding 225 MHz
- Counter speeds over 200 MHz
產(chǎn)品屬性
- 型號:
QL2003
- 功能描述:
3.3V and 5.0V pASIC-R 2 FPGA Combining Speed, Density, Low Cost and Flexibility
供應(yīng)商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價格 |
---|---|---|---|---|---|---|---|
QUICKLO |
2020+ |
QFP100 |
80000 |
只做自己庫存,全新原裝進口正品假一賠百,可開13%增 |
詢價 | ||
QUICKLOGIC |
23+ |
QFP100 |
20000 |
原廠原裝正品現(xiàn)貨 |
詢價 | ||
QUICKLOGI |
21+ |
TQFP |
35200 |
一級代理/放心采購 |
詢價 | ||
QUICKLOCOM |
QFP |
8540 |
只做原裝貨值得信賴 |
詢價 | |||
2023+ |
QFP100 |
80000 |
一級代理/分銷渠道價格優(yōu)勢 十年芯程一路只做原裝正品 |
詢價 | |||
QULCKLOGIC |
05+ |
PLCC84 |
58 |
一級代理,專注軍工、汽車、醫(yī)療、工業(yè)、新能源、電力 |
詢價 | ||
QUALCOMM |
23+ |
TQFP |
4500 |
全新原裝、誠信經(jīng)營、公司現(xiàn)貨銷售 |
詢價 | ||
QULCKLOGIC |
2048+ |
PLCC84 |
9852 |
只做原裝正品現(xiàn)貨!或訂貨假一賠十! |
詢價 | ||
QLOG |
23+ |
65480 |
詢價 | ||||
QVICKLOGIC |
23+ |
PLCC84 |
7000 |
絕對全新原裝!100%保質(zhì)量特價!請放心訂購! |
詢價 |
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