PM5313中文資料PMC數(shù)據(jù)手冊(cè)PDF規(guī)格書

DESCRIPTION

The PM5313 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER (SPECTRA-622) terminates the transport and path overhead of STS-12 (STM-4/AU3 or STM- 4/AU4) and STS-12c (STM-4-4c) streams at 622.08 Mbit/s. The SPECTRA-622 implements significant functions for a SONET/SDH compliant line interface, as well as DS3 mapping.

FEATURES

General

? Monolithic SONET/SDH PAYLOAD EXTRACTOR/ALIGNER for use in STS-12 (STM-4/AU3 or STM-4/AU4) or STS-12c (STM-4-4c) interface applications, operating at serial interface speeds of up to 622.08 Mbit/s.

? Provides integrated clock and data recovery and clock synthesis for direct connection to optical modules.

? Supports a duplex byte-serial 77.76 Mbyte/s STS-12 (STM-4/AU3 or STM-4/AU4) or STS-12c (STM-4-4c) line side interface for use in applications where by-passing clock recovery, clock synthesis, and serializer-deserializer functionality is desired.

? Supports clock recovery bypass for use in applications where external clock recovery is desired.

? Complies with Bellcore GR-253-CORE jitter tolerance (1995 issue), jitter transfer and intrinsic jitter criteria.

? Provides control circuitry to comply with Bellcore GR-253-CORE WAN clocking requirements related to wander transfer, holdover and long term stability when using an external VCXO.

? Provides termination for SONET Section and Line, SDH Regenerator Section and Multiplexer Section transport overhead, and path overhead of twelve STS-1 (STM-0/AU3) paths, four STS-3/3c (STM-1/AU3/AU4) paths or a single STS-12c (STM-4-4c) path.

? De-multiplexes an STM-4 receive stream to four STM-1 Telecom DROP bus streams.

? Multiplexes four STM-1 Telecom ADD bus streams to an STM-4 transmit stream.

? Maps twelve STS-1 (STM-0/AU3) payloads, four STS-3/3c (STM-1/AU3/AU4) payloads or a single STS-12c (STM-4-4c) payload to system timing reference, accommodating plesiochronous timing offsets between the references through pointer processing.

? Maps twelve DS3 bit streams into an STS-12 (STM-4/AU3) frame.

? Provides Time Slot Interchange (TSI) function at the Telecom ADD and DROP buses for grooming twelve STS-1 (STM-0/AU3) paths or four STS-3/3c (STM-1/AU3/AU4) paths.

? Supports line loopback from the line side receive stream to the transmit stream and diagnostic loopback from a Telecom ADD bus interface to a Telecom DROP bus interface.

? Supports OC-48(STM-16) applications by providing parallel receive and transmit line side ports used to connect to front-end OC-48 devices.

? Provides a standard 5 signal IEEE 1149.1 JTAG test port for boundary scan board test purposes.

? Provides a generic 8-bit microprocessor bus interface for configuration, control, and status monitoring.

? Low power 3.3V CMOS with TTL compatible digital inputs and CMOS/TTL digital outputs. PECL inputs and outputs are 3.3V and 5V compatible.

? Industrial temperature range (-40°C to +85°C).

? 520 pin Super BGA package.

APPLICATIONS

? SONET/SDH Add Drop Multiplexers

? SONET/SDH Terminal Multiplexers

? SONET/SDH Line Multiplexers

? SONET/SDH Cross Connects

? SONET/SDH Test Equipment

? Switches and Hubs

? Routers