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      PLL103-06XI中文資料PLL數(shù)據(jù)手冊PDF規(guī)格書

      PLL103-06XI
      廠商型號

      PLL103-06XI

      功能描述

      DDR SDRAM Buffer with 2 DDR or 3 SDRAM DIMMS

      文件大小

      145.87 Kbytes

      頁面數(shù)量

      7

      生產(chǎn)廠商 PhaseLink Corporation
      企業(yè)簡稱

      PLL

      中文名稱

      PhaseLink Corporation官網(wǎng)

      原廠標(biāo)識
      數(shù)據(jù)手冊

      下載地址一下載地址二

      更新時間

      2024-11-17 10:36:00

      PLL103-06XI規(guī)格書詳情

      DESCRIPTIONS

      The PLL103-06 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 12 outputs. These outputs can be configured to support 3 unbuffered standard SDR (Single Data Rate) DIMMS and 2 DDR DIMMS. The PLL103-06 can be used in conjunction with the PLL202-04 or similar clock synthesizer for the VIA Pro 266 chipset.

      FEATURES

      ? Generates 12-output buffers from one input.

      ? Supports up to 2 DDR DIMMS or 3 SDRAM DIMMS.

      ? Supports 266MHz DDR SDRAM.

      ? One additional output for feedback.

      ? Less than 5ns delay.

      ? Skew between any outputs is less than 100 ps.

      ? 2.5V or 3.3V Supply range.

      ? Enhanced DDR and SDRAM Output Drive selected by I2C.

      ? Available in 28 pin SSOP.

      產(chǎn)品屬性

      • 型號:

        PLL103-06XI

      • 制造商:

        PLL

      • 制造商全稱:

        PLL

      • 功能描述:

        DDR SDRAM Buffer with 2 DDR or 3 SDRAM DIMMS

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