PIMXRT1183CVJ8A中文資料恩智浦?jǐn)?shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

Features

The i.MX RT1180 processors are based on Arm? Cortex?-M7 Core? Platform, which has the

following features:

? The Arm Cortex-M7 Core Platform:

— 32 KB L1 Instruction Cache and 32 KB L1 Data Cache

— Floating Point Unit (FPU) with single-precision and double-precision supports of the

Armv7-M architecture FPv5

— Support the Armv7-M Thumb instruction set, defined in the Armv7-M architecture

— Integrated Memory Protection Unit (MPU), up to 16 individual protection regions

— Up to 512 KB I-TCM and D-TCM in total

— Frequency of 800 MHz at 1.1 V (over drive) with Forward Body Biasing (FBB)

— ECC support for both Cache and Tightly Coupled Memory (TCM)

— Frequency of the core, as per Table 11, Operating ranges, on page 26.

? The Arm Cortex-M33 Core platform:

— Micro-controller available both for boot and customer application

— 16 KB Code Cache, 16 KB System Cache, and 256 KB TCM (also accessible as SRAM by the

rest of the system)

— Frequency is 240 MHz at 1.0 V without body biasing

— ECC support for both Cache and TCM

? On-chip memory:

— Boot ROM (160 KB)

— 512 KB TCM for CM7 with ECC

— 256 KB TCM for CM33 with ECC

— Dedicated 768 KB OCRAM with ECC

? External memory interfaces:

— Smart External Memory Controller (SEMC)

– 8/16/32-bit SDRAM interface, 4 Chip Selects (CS) and each CS up to 1024 Mb

– 8/16-bit NAND FLASH interface with hardware ECC

– 8/16-bit NOR FLASH interface

– SRAM: supports SRAM and Pseudo SRAM, 8-bit and 16-bit modes, ADMUX, AADM,

and Non-ADMUX modes, up to 4 CS, up to 4096 Mb memory size

— 2x FlexSPI

– Single/Dual channel Quad SPI FLASH with XIP support

– Hyper RAM/FLASH

– PSRAM

– OCT RAM/FLASH

– OTFAD is supported for decryption with 0 cycle delay

Each i.MX RT1180 processor enables the following interfaces to external devices (some of them are

muxed and not available simultaneously):

? Audio:

— 1x SPDIF input and output

— 4x Synchronous Audio Interface (SAI) modules supporting I2S, AC97, TDM, and codec/DSP

interfaces

— Digital microphone input, 8-channel PDM

— Asynchronous Sample Rate Converter (ASRC)

? Connectivity:

— 2x USB 2.0 OTG controllers with integrated PHY interfaces

— 2x Ultra Secure Digital Host Controller (uSDHC) interfaces

– uSDHC2 with boot support for eMMC 5.1 compliance with HS400 DDR signaling to

support up to 400 MB/sec

– uSDHC1 with boot support for SD/SDIO 3.0 compliance with 200 MHz SDR signaling to

support up to 100 MB/sec

– Support for SDXC (extended capacity)

— 12x low power universal asynchronous receiver/transmitter (LPUARTs) modules

— 6x LPI2C modules

— 2x I3C modules

— 6x LPSPI modules

— 3x Control Area Network (FlexCAN) modules, each with support in hardware to support

Flexible Datarate (FD), with enhanced RX FIFO.

— 2x FlexIO modules

— Advanced and flexible Ethernet

– Third version of NXP TSN switch IP (NETC 3.0)

– Port virtualization support on ENETC0 MAC for dual Access (CM33/CM7)

– Extended support of TSN standards over flexible architecture

– 1x independent 1 Gbps TSN MAC endpoint

– 5-port (4 external + 1 internal) TSN Switch with 1 Gbps TSN MAC

– OPC UA Frame Summation HW acceleration integrated in switch

– Up to 5 RGMII/MII/RMII external ports

? ADC/CMP

— 2x 16-bit dual-channel SAR ADC (16 channels on ADC1 and 14 channels on ADC2), 3.5

Msps, each ADC can proceed 2 conversions simultaneously

— 1x 12-bit DAC

— 4x Analog Comparators (ACMP)

— 3x SINC filters (4-channel) to interface to external sigma-delta ADC

— Voltage Reference (VREF)

? GPIO and Pin Multiplexing:

— General-purpose input/output (GPIO) modules with interrupt capability

— Input/output multiplexing controller (IOMUXC) to provide centralized pad control

The i.MX RT1180 processors integrate advanced power management unit and controllers:

? Full PMIC integration, including on-chip DCDC and LDOs

? Temperature sensor with programmable trim points

? GPC Hardware power management controller

? Timers and PWMs:

— 2x General Programmable Timer (GPT) modules

– 4-channel generic 32-bit resolution timer for each

– Each supports standard capture and compare operation

— 3x Low Power Periodical Interrupt Timer (LPIT) modules

– 4-channel

– 4 external trigger sources

– Generic 32-bit resolution timer

– Periodical interrupt generation

— 6x Timer/PWM modules (TPM)

– Prescaler divide-by 1, 2, 4, 8, 16, 32, 64, or 128

– 16-bit counter, support free-running counter or modulo counter mode, counting up or down

– Includes 6 channels that can be configured for input capture, output compare, edge-aligned

PWM mode, or center-aligned PWM mode

— 3x Low-Power Timer (LPTMR) modules

— 8x Quad Timer (TMR) modules

– 4-channel generic 16-bit resolution timer for each

– Each supports standard capture and compare operation

– Enhanced Quadrature decoder integrated

— 4x FlexPWM modules

– Up to 8 individual PWM channels for each

– 16-bit resolution PWM suitable for Motor Control applications

— 4x Enhanced Quadrature Decoders (eQDC)

— 6x Watchdog Timer (WDOG)

– 1x for the Cortex-M33 non-secure, 1x for Cortex-M33 secure, 1x for the Cortex-M7 and 2x

additional for customer usage

– 1x External Watchdog Monitor (EWM)

The i.MX RT1180 processors support the following system debug:

? Arm Cortex-M7 CoreSight? debug and trace architecture

? CoreSight Serial Wire Output (SWO) and Embedded Trace Router (ETR) can allow routing trace

data to system memory

? Support for 5-pin (JTAG) and SWD debug interfaces

Security functions are enabled and accelerated by the following hardware:

? Trusted Resource Domain Controller (TRDC)

— Supports up to 16 resource domains

? TrustZone?-M (TZ-M) on Cortex-M33

? Physical Unclonable Function (PUF)

? EdgeLock? secure enclave

— Advanced security: AES, AES-GCM, PKA, ECDSA/ECDH, TRNG, AES-256, SHA, DES,

3DES, RSA4096, ECC1024, UniqueID, Secure Boot, Secure RTC, Tamper Monitor

— Public Key co-processor

— Symmetric Crypto Accelerators

— Random number generator

— One-Time Programmable electrical fuse used for security keys and configuration other security

related functions

— Physically Unclonable Function based master secrets as an option

? Battery Backed Security Module (BBSM)

— Monotonic counter

— Secure real-time clock (RTC)

— Zeroizable Master Key

? Inline Encryption Engine (IEE)

— External memory encryption and decryption

— I/O direct encrypted storage and retrieval (Stream Support)

? On-The-Fly AES Decryption (OTFAD)

— Support OTFAD with 4 keys