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PIC16F17154中文資料微芯科技數(shù)據(jù)手冊PDF規(guī)格書
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PIC16F17154規(guī)格書詳情
Core Features
? C Compiler Optimized RISC Architecture
? Operating Speed:
– DC – 32 MHz clock input
– 125 ns minimum instruction time
? 16-Level Deep Hardware Stack
? Low-Current Power-on Reset (POR)
? Configurable Power-up Timer (PWRT)
? Brown-out Reset (BOR)
? Low-Power Brown-out Reset (LPBOR)
? Windowed Watchdog Timer (WWDT)
