Introduction

The Smart Integrated Digital Echo Canceller (SIDEC) suppresses echoes in telecommunication networks which might disturb any kind of terrestrial or wireless communication. It incorporates leading edge CMOS technology as well as INFINEON’s many years experience in Telecommunication ICs.

Key Features

? 2.048 MHz PCM input and output interfaces with selectable μ- and A-Law coding according to ITU G.711

? Rapid convergence of patented algorithm at the beginning or during a connection even in the presence of background noise at the near end subscriber

? Echo return loss enhancement of > 30 dB (ERLE)

? Detection of double talk for adaptive convergence control

? Independently controlled voiceband echo cancelling according to ITU G.165 and G.168 for

??? – 32 channels with end echo path delay of less than 63.75 ms

??? – 16 channels with end echo path delay of less than 127.75 ms (usage of two SIDEC in parallel for simultaneous processing of 32 channels is easily possible)

? Smart Non Linear Processor controlled by echoloss, echo path delay and background noise

? Various options for comfort noise injection

? Maskable disabling functions

??? – 2100 Hz tone with phase reversal detection

??? – 2100 Hz tone without phase reversal detection

??? – 2010 Hz continuity check (SS7)

??? – via PCM timeslot 16 Bit a, b, c or d according to ITU G.704

??? – individual channels maskable via Microprocessor Interface, UCC Interface and Serial Interface

? Integrated Universal Control and Communication Interface (UCCI) for signaling highways with direct hardware control for:

??? – disable cancelling

??? – configurable disabling functions

??? – communication between board controllers

? Support of Channel Associated Signaling (CAS) BR transparency (robbed bits) in send path

? Selectable μ- to A-Law or A- to μ-Law Conversion on a global or per channel basis

? Configurable idle channel supervision

? Clear channel capability (64 clear) on a per channel basis

? Special evaluation of bit 8 in T1 Modem calls possible (56 clear)

? Serial 256 kbit/s interface to control the functions disable cancelling, freeze coefficients, clear channel, disable NLP, PCM Law conversion control or combinations of above

? Monitor pins for several internal states

? Switchable global loop from receive output to send input and send output to receive input

? Switchable global attenuation (2.5 dB or 6 dB) at the receive and send output

? Flexible Microprocessor Interface (Intel or Motorola type, Mux and Demux mode) usable for:

??? – configuration of parameters such as thresholds and functions on a global basis

??? – Disable cancelling, freeze coefficients, clear channel, disable NLP, PCM Law conversion control (all functions individually for each channel)

??? – support of background tests for disabled or idle timeslots (feeding and reading of test levels)

??? – possibility to read levels, attenuations, internal states, signal values or all coefficients of a selected timeslot

??? – control of the RAM Built In Self Test

? Advanced Integrated Watchdog Timer

? Supervision of the input clocks

? Various clock modes possible for 32.768 MHz and 8.192 MHz

? Boundary Scan according to IEEE 1149.1 Standard

? Power supply: 3.3 V, 5V tolerant inputs

? Typical power dissipation: 900 mW

? Plastic package P-TQFP 144-8, P-LFBGA 160-2

? Temperature range: -40°C - 85°C and 0°C - 70°C