PCLV165BMPWREP中文資料德州儀器數(shù)據(jù)手冊PDF規(guī)格書

1 Features

? 2 V to 5.5 V VCC operation

? Maximum tpd of 10.5 ns at 5 V

? Supports mixed-mode voltage operation

on all ports

? Ioff supports partial-power-down mode operation

? Latch-up performance exceeds 250 mA

per JESD 17

? Operating ambient temperature: -55°C to +125°C

? Supports defense, aerospace, and medical

applications:

– Controlled baseline

– One assembly and test site

– One fabrication site

– Extended product life cycle

– Product traceability

2 Applications

? Increase the number of inputs on a microcontroller

3 Description

The SN74LV165B-EP device is a parallel-load, 8-bit

shift registers designed for 2 V to 5.5 V VCC operation.

When the device is clocked, data is shifted toward the

serial output QH. Parallel-in access to each stage is

provided by eight individual direct data inputs that are

enabled by a low level at the shift/load (SH/ LD) input.

The SN74LV165B-EP devices features a clock-inhibit

function and a complemented serial output, Q H.

This device is fully specified for partial-power-down

applications using Ioff. The Ioff circuitry disables

the outputs, preventing damaging current backflow

through the devices when they are powered down.