General description

The PCA9525 is a monolithic CMOS integrated circuit for bus buffering in applications including I2C-bus, SMBus, DDC, PMBus,and other systems based on similar principles.

The buffer extends the bus load limit by buffering both the SCL and SDA lines, allowing the maximum permissible bus capacitance on both sides of the buffer.

The PCA9525 includes a unidirectional buffer for the clock signal, and a bidirectional buffer for the data signal. Slave devices which employ clock stretching are therefore not supported.

Features and benefits

Simple impedance isolating buffer for 2-wire buses

4 mA maximum static open-drain pull-down capability supports a wide range of bus standards

Works with I2C-bus (Standard-mode, Fast-mode), SMBus (standard and high power mode), and PMBus

Fast switching times allow operation in excess of 1 MHz

Enable allows bus segments to be disconnected

Hysteresis on inputs provides noise immunity

Operating voltages from 2.7 V to 5.5 V

Very low supply current

Uncomplicated characteristics suitable for quick implementation in most common 2-wire bus applications

Applications

Electronic signs and displays

Game consoles/boxes

Gaming machine networks

TV/projector/monitor interconnection (DDC)

Power management systems

Desktop and portable computers

Security systems

PCA9525D屬于集成電路（IC） > 信號緩沖器、中繼器、分離器。恩智浦半導(dǎo)體公司制造生產(chǎn)的PCA9525D信號緩沖器、中繼器、分離器信號緩沖器、中繼器和分離器系列中的產(chǎn)品適用于遠(yuǎn)距離電氣互連或電纜系統(tǒng)的數(shù)字信息傳輸。所有實際互連系統(tǒng)都具有非理想特性，該系列產(chǎn)品主要用于解決數(shù)字信息傳輸過程中因此造成的模擬問題。此外，還有其他功能，例如不同物理接口樣式之間的轉(zhuǎn)換和多路復(fù)用。