PCA9515D集成電路（IC）的信號緩沖器、中繼器、分離器規(guī)格書PDF中文資料

General description

The PCA9515 is a BiCMOS integrated circuit intended for application in I2C-bus and SMBus systems.

While retaining all the operating modes and features of the I2C-bus system, it permits extension of the I2C-bus by buffering both the data (SDAn) and the clock (SCLn) lines, thus enabling two buses of 400 pF.

The I2C-bus capacitance limit of 400 pF restricts the number of devices and bus length. Using the PCA9515 enables the system designer to isolate two halves of a bus, thus more devices or longer length can be accommodated. It can also be used to run two buses, one at 5 V and the other at 3.3 V or a 400 kHz and 100 kHz bus, where the 100 kHz bus is isolated when 400 kHz operation of the other is required.

Features

■ 2 channel, bidirectional buffer

■ I2C-bus and SMBus compatible

■ Active HIGH repeater enable input

■ Open-drain input/outputs

■ Lock-up free operation

■ Supports arbitration and clock stretching across the repeater

■ Accommodates Standard-mode and Fast-mode I2C-bus devices and multiple masters

■ Powered-off high-impedance I2C-bus pins

■ Operating supply voltage range of 3.0 V to 3.6 V

■ 5.5 V tolerant I2C-bus (SCLn, SDAn) and enable (EN) pins

■ 0 Hz to 400 kHz clock frequency1

■ ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101

■ Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

■ Packages offered: SO8 and TSSOP8 (MSOP8)