PA7572J-20中文資料易亨電子數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

General Description

The PA7572 is a member of the Programmable Electrically Erasable Logic (PEEL?) Array family based on Anachip’s CMOS EEPROM technology. PEEL? Arrays free designers from the limitations of ordinary PLDs by providing the architectural flexibility and speed needed for today’s programmable logic designs. The PA7572 offers a versatile logic array architecture with 24 I/O pins, 14 input pins and 60 registers/latches (24 buried logic cells, 12 input registers/latches, 24 buried I/O registers/latches). Its logic array implements 100 sum-of-products logic functions divided into two groups each serving 12 logic cells. Each group shares half (60) of the 120 product-terms available.

Versatile Logic Array Architecture

- 24 I/Os, 14 inputs, 60 registers/latches

- Up to 72 logic cell output functions

- PLA structure with true product-term sharing

- Logic functions and registers can be I/O-buried

High-Speed Commercial and Industrial Versions

- As fast as 13ns/20ns (tpdi/tpdx), 66.6MHz (fMAX)

- Industrial grade available for 4.5 to 5.5V VCC and -40 to +85 °C temperatures

Ideal for Combinatorial, Synchronous and Asynchronous Logic Applications

- Integration of multiple PLDs and random logic

- Buried counters, complex state-machines

- Comparators, decoders, other wide-gate functions

CMOS Electrically Erasable Technology

- Reprogrammable in 40-pin DIP, 44-pin PLCC and TQFP packages

Flexible Logic Cell

- Up to 3 output functions per logic cell

- D,T and JK registers with special features

- Independent or global clocks, resets, presets, clock polarity and output enables

- Sum-of-products logic for output enables

Development and Programmer Support

- ICT PLACE Development Software

- Fitters for ABEL, CUPL and other software

- Programming support by popular third-party programmers