P102-10SC中文資料PLL數(shù)據(jù)手冊(cè)PDF規(guī)格書
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DESCRIPTION
The PLL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC or MSOP package. It has two outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than ±350 ps, the device acts as a zero delay buffer.
FEATURES
? Frequency range 50 ~ 120MHz.
? Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to outputs.
? Zero input - output delay.
? Less than 700 ps device - device skew.
? Less than 250 ps skew between outputs.
? Less than 100 ps cycle - cycle jitter.
? 2.5V or 3.3V power supply operation.
? Available in 8-Pin SOIC or MSOP package.
產(chǎn)品屬性
- 型號(hào)：
P102-10SC
- 制造商：
PLL
- 制造商全稱：
PLL
- 功能描述：
Low Skew Output Buffer
| 供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
NXP/恩智浦 |
21+ |
TEPBGA-689 |
6000 |
原裝現(xiàn)貨 |
詢價(jià) | ||
NXP/恩智浦 |
23+ |
TEPBGA-689 |
30000 |
原裝正品公司現(xiàn)貨,假一賠十! |
詢價(jià) | ||
NXP/恩智浦 |
23+ |
TEPBGA-689 |
6982 |
原廠原裝正品現(xiàn)貨,代理渠道,支持訂貨!!! |
詢價(jià) | ||
FREESCAL |
23+ |
BGAQFP |
8659 |
原裝公司現(xiàn)貨!原裝正品價(jià)格優(yōu)勢(shì). |
詢價(jià) | ||
NXP/恩智浦 |
21+ |
TEPBGA-689 |
8080 |
只做原裝,質(zhì)量保證 |
詢價(jià) | ||
TI |
23+ |
SOP8 |
4500 |
全新原裝、誠信經(jīng)營、公司現(xiàn)貨銷售! |
詢價(jià) | ||
TI |
24+ |
SOP8 |
203 |
詢價(jià) | |||
NXP(恩智浦) |
2112+ |
TEPBGAII-689(31x31) |
31500 |
27個(gè)/托盤一級(jí)代理專營品牌!原裝正品,優(yōu)勢(shì)現(xiàn)貨,長(zhǎng) |
詢價(jià) | ||
恩智浦 |
22+ |
NA |
500000 |
萬三科技,秉承原裝,購芯無憂 |
詢價(jià) | ||
NXP/恩智浦 |
23+ |
TEPBGA-689 |
6000 |
只做原裝,實(shí)單可談 |
詢價(jià) |
