NAND512W3A2BZA6E集成電路（IC）的存儲(chǔ)器規(guī)格書(shū)PDF中文資料

NAND512W3A2BZA6E屬于集成電路（IC）的存儲(chǔ)器。由意法半導(dǎo)體集團(tuán)制造生產(chǎn)的NAND512W3A2BZA6E存儲(chǔ)器存儲(chǔ)器是集成電路上用作數(shù)據(jù)存儲(chǔ)設(shè)備的半導(dǎo)體器件。這些器件分為非易失性或易失性?xún)煞N，格式包括 CBRAM、DRAM、EEPROM、EERAM、EPROM、閃存、FRAM、NVSRAM、PCM (PRAM)、PSRAM、RAM 和 SRAM。這些器件的存儲(chǔ)容量為 64 b 至 6 Tb 不等，接口有 I2C、MMC、并行、eMMC、串行、單線(xiàn)、SPI、UFS、Xccela 總線(xiàn)和 1-線(xiàn)。

SUMMARY DESCRIPTION

The NAND Flash 528 Byte/ 264 Word Page is a family of non-volatile Flash memories that uses

the Single Level Cell (SLC) NAND cell technology. It is referred to as the Small Page family. The devices range from 128Mbits to 1Gbit and operate with either a 1.8V or 3V voltage supply. The size of a Page is either 528 Bytes (512 + 16 spare) or 264 Words (256 + 8 spare) depending on whether the device has a x8 or x16 bus width.

FEATURES SUMMARY

■ HIGH DENSITY NAND FLASH MEMORIES

– Up to 1 Gbit memory array

– Up to 32 Mbit spare area

– Cost effective solutions for mass storage applications

■ NAND INTERFACE

– x8 or x16 bus width

– Multiplexed Address/ Data

– Pinout compatibility for all densities

■ SUPPLY VOLTAGE

– 1.8V device: VDD = 1.7 to 1.95V

– 3.0V device: VDD = 2.7 to 3.6V

■ PAGE SIZE

– x8 device: (512 + 16 spare) Bytes

– x16 device: (256 + 8 spare) Words

■ BLOCK SIZE

– x8 device: (16K + 512 spare) Bytes

– x16 device: (8K + 256 spare) Words

■ PAGE READ / PROGRAM

– Random access: 12μs (max)

– Sequential access: 50ns (min)

– Page program time: 200μs (typ)

■ COPY BACK PROGRAM MODE

– Fast page copy without external buffering

■ FAST BLOCK ERASE

– Block erase time: 2ms (Typ)

■ STATUS REGISTER

■ ELECTRONIC SIGNATURE

■ CHIP ENABLE ‘DON’T CARE’ OPTION

– Simple interface with microcontroller

■ SERIAL NUMBER OPTION

■ HARDWARE DATA PROTECTION

– Program/Erase locked during Power transitions

■ DATA INTEGRITY

– 100,000 Program/Erase cycles

– 10 years Data Retention

■ RoHS COMPLIANCE

– Lead-Free Components are Compliant with the RoHS Directive

■ DEVELOPMENT TOOLS

– Error Correction Code software and hardware models

– Bad Blocks Management and Wear Leveling algorithms

– File System OS Native reference software

– Hardware simulation models