MV1442IG中文資料ZARLINK數(shù)據(jù)手冊PDF規(guī)格書

HDB3 Encoder/Decoder/Clock Regenerator

The MV1442, along with other devices in the Zarlink 2Mbit PCM signalling series comprise a group of circuits which will perform the common channel signalling and error detection functions for a 2.048Mbit PCM transmission link operating in accordance with the appropriate CCITT recommendations. The circuits are fabricated in CMOS and operate from a single +5V supply with all inputs and outputs being TTL compatible.

Features

? On-chip Digital Clock Regenerator

? HDB3 Encoding and Decoding to CCITT Recommendation G.703

? Asynchronous Operation

? Simultaneous Encoding and Decoding

? Clock Recovery Signal allows Off-chip Clock Regeneration

? Loop Back Control

? HDB3 Error Monitor

? ‘All Ones’ Error Monitor

? Loss of Input Alarm

? Low Power Operation

? 2.048MHz or 1.544MHz Operation in External or Internal Clock Recovery mode

? 8.448MHz Operation in External Clock Recovery mode