MU9C8328A-RDC中文資料MUSIC數(shù)據(jù)手冊(cè)PDF規(guī)格書

GENERAL DESCRIPTION

The MU9C8328A speeds up bridging operations using Ethernet controller chips with serial NRZ data outputs, such as AMD’s MACE?, National’s SONIC?, and Motorola’s QUICC? controllers, by parsing the Ethernet frame independently of the Ethernet controller device, and notifying it whether to accept or reject the incoming frame. The MU9C8328A supports both positive and negative filtering on the Destination address and learning of new Source addresses, by efficiently controlling the compare activities of the MUSIC LANCAM Family. Filtering and learning routines are user configurable. These routines are automatically invoked by the internal state machine based on the contents of the incoming frame and the configuration settings. For aging and other housekeeping routines, the MU9C8328A provides the proper sequencing and timing of LANCAM accesses for an external processor.

APPLICATION BENEFITS

? Single port 10 MHz Ethernet address parsing, filtering, and learning at wire speed

? Glue-free interface between the MUSIC LANCAM? Family and AMD, National, Motorola, or similar Ethernet Controllers having an NRZ serial data port

? Selectable filtering and learning decisions on DA and SA compares

? Supports aging with built-in LRU purge routine

? Supports cascaded MUSIC LANCAM series for long station lists

? Host processor port for LANCAM initialization and housekeeping activities

? Supports system clock rates from 20 MHz to 33 MHz

? Compatible with MU9C8328

? 100-pin PQFP package

? 5 Volt operation