MT90866AG2集成電路（IC）的電信規(guī)格書PDF中文資料

Description

The MT90866 Digital Switch provides switching capacities of 4,096 x 2,432 channels between backplane and local streams, 2,432 x 2,432 channels among local streams and 2,048 x 2,048 channels among backplane streams. The local connected serial inputs and outputs have 32, 64 and 128 64 kb/s channels per frame with data rates of 2.048, 4.096 and 8.192 Mb/s respectively. The backplane connected serial inputs and outputs have 128 and 256 64 kb/s channels per frame with data rates of 8.192 and 16.384 Mb/s respectively.

Features

? 2,432 x 2,432 non-blocking switching among local streams

? 4,096 x 2,432 blocking switching between backplane and local streams

? 2,048 x 2,048 non-blocking switching among backplane streams

? Rate conversion between backplane and local streams

? Rate conversion among local streams

? Backplane interface accepts data rates of 8.192 Mb/s or 16.384 Mb/s

? Local interface accepts data rates of 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s

? Sub-rate switching (2 or 4 bits) configuration for local streams at a data rate of 2.048 Mb/s

? Meets all the key H.110 mandatory signal requirements including timing

? Per-channel variable or constant throughput delay

? Per-stream input delay, programmable for local streams on a per bit basis

? Per-stream output advancement, programmable for backplane and local streams

? Per-channel direction control for backplane streams

? Per-channel message mode for backplane and local streams

? Per-channel high impedance output control for backplane and local streams

? Compatible to Stratum 4 Enhanced clock switching standard

- Integrated PLL conforms to Telcordia GR-1244- CORE Stratum 4 Enhanced switching standard

- Holdover Mode with holdover frequency stability of 0.07 ppm

- Jitter attenuation from 1.52 Hz.

- Time interval error (TIE) correction

- Master and Slave mode operation

? Non-multiplexed microprocessor interface

? Connection memory block-programming for fast device initialization

? Tristate-control outputs for external drivers

? Pseudo-Random Binary Sequence (PRBS) pattern generation and testing for backplane and local streams

? Conforms to the mandatory requirements of the IEEE-1149.1 (JTAG) standard

? 3.3V operation with 5 V tolerant inputs and I/O’s

? 5 V tolerant PCI driver on CT-Bus I/O’s

Applications

? Carrier-grade VoIP Gateways

? IP-PBX and PABX

? Integrated Access Devices

? Access Servers

? CTI Applications/CompactPCI? Platforms

? H.110, H.100, ST-BUS and proprietary Backplane Applications