MT54W4MH9B中文資料鎂光數(shù)據(jù)手冊(cè)PDF規(guī)格書

4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36 1.8V VDD, HSTL, QDRIIb2 SRAM

GENERAL DESCRIPTION

The Micron? QDR?II (Quad Data Rate?) synchronous, pipelined burst SRAM employs high-speed, low power CMOS designs using an advanced 6T CMOS process.

The QDR architecture consists of two separate DDR (double data rate) ports to access the memory array. The read port has dedicated data outputs to support READ operations. The write port has dedicated data inputs to support WRITE operations. This architecture eliminates the need for high-speed bus turnaround. Access to each port is accomplished using a common address bus. Addresses for reads and writes are latched on rising edges of the K and K# input clocks, respectively. Each address location is associated with two words that burst sequentially into or out of the device.

FEATURES

? DLL circuitry for accurate output data placement

? Separate independent read and write data ports with concurrent transactions

? 100 percent bus utilization DDR READ and WRITE operation

? Fast clock to valid data times

? Full data coherency, providing most current data

? Two-tick burst counter for low DDR transaction size

? Double data rate operation on read and write ports

? Two input clocks (K and K#) for precise DDR timing at clock rising edges only

? Two output clocks (C and C#) for precise flight time and clock skew matching—clock and data delivered together to receiving device

? Single address bus

? Simple control logic for easy depth expansion

? Internally self-timed, registered writes

? +1.8V core and HSTL I/O

? Clock-stop capability

? 15mm x 17mm, 1mm pitch, 11 x 15 grid FBGA package

? User-programmable impedance output

? JTAG boundary scan