MPC2005中文資料摩托羅拉數(shù)據(jù)手冊(cè)PDF規(guī)格書

The MPC2004 and MPC2005 are designed to provide burstable, high performance 256KB/512KB L2 cache for the PowerPC 60x microprocessor family in conformance with the PowerPC Reference Platform (PReP) and the PowerPC Common Hardware Reference Platform (CHRP) specifications. The modules are configured as 32K x 72 and 64K x 72 bits in a 182 (91 x 2) pin DIMM format. Each module uses four of Motorola’s 5 V 32K x 18 or 64K x 18 BurstRAMs and a 5 V cache tag RAM configured as 16K x 12 for tag field plus 16K x 2 for valid and dirty status bits.

? PowerPC–style Burst Counter on Chip

? Flow–Through Data I/O

? Module Requires Both 3.3 V and 5 V Power Supplies

? Multiple Clock Pins for Reduced Loading

? All Cache Data and Tag I/Os are LVTTL (3.3 V) Compatible

? Three State Outputs

? Byte Write Capability

? Fast Module Clock Rates: 66 MHz

? Fast SRAM Access Times: 10 ns for Tag RAM Match 9 ns for Data RAM

? Decoupling Capacitors for Each Fast Static RAM

? High Quality Multi–Layer FR4 PWB With Separate Power and Ground Planes

? 182 Pin Card Edge Module

? Burndy Connector, Part Number: ELF182JSC–3Z50