GENERAL DESCRIPTION

The MEC172x is a family of low power integrated embedded controller designed for notebook applications storage

enclosure platforms. The MEC172x is a highly-configurable, mixed-signal, advanced I/O controller. It contains a 32-bit

ARM? Cortex-M4F processor core with closely-coupled memory for optimal code execution and data access. An internal

ROM, embedded in the design, is used to store the power on/boot sequence and APIs available during run time.

When VTR_CORE is applied to the device, the secure bootloader API is used to download the custom firmware image

from the system’s shared SPI Flash device, thereby allowing system designers to customize the device’s behavior.

The MEC172x device is directly powered by a minimum of two separate suspend supply planes (VBAT and VTR) and

senses a third runtime power plane (VCC) to provide “instant on” and system power management functions. The

MEC172x has one banks of I/O pins that are able to operate at 3.3 V (VTR1), one bank that is 1.8V (VTR3) and one

bank that can operate at 3.3V/1.8V (VTR2). Operating at 1.8V allows the MEC172x to interface with the latest platform

controller hubs and will lower the overall power consumed by the device, Whereas 3.3V allows this device to be integrated

into legacy platforms that require 3.3V operation.

The MEC172x host interface is the Intel? Enhanced Serial Peripheral Interface (eSPI). The eSPI Interface is a 1.8V

interface that operates in single, double and quad I/O modes. The eSPI Interface supports all four eSPI channels:

Peripheral Channel, Virtual Wires Channel, OOB Message Channel, and Run-time Flash Access Channel. The eSPI

hardware Flash Access Channel is used by the Boot ROM to support Master Attached Flash Sharing (MAFS). In addition,

the MEC172x has specially designed hardware to support Slave Attached Flash Sharing (SAFS). The eSPI SAFS

Bridge imposes Region-Based Protection and Locking security feature, which limits access to certain regions of the

flash to specific masters. There may be one or more masters (e.g., BIOS, ME, etc) that will access the SAF via the eSPI

interface. The ARM? Cortex-M4F processor is also considered a master, which will also have its access limited to EC

only regions of SPI Flash as determined by the customer firmware application.The MEC172x secure bootloader authenticates

and optionally decrypts the SPI Flash OEM boot image using the AES-256, ECDSA, SHA-512 cryptographic

hardware accelerators. The MEC172x hardware accelerators support 128-bit and 256-bit AES encryption, ECDSA and

EC_KCDSA signing algorithms, 1024-bits to 4096-bits RSA and Elliptic asymmetric public key algorithms, and a True

Random Number Generator (TRNG). Runtime APIs are provided in the ROM for customer application code to use the

cryptographic hardware. Additionally, the device offers lockable OTP storage for private keys and IDs.

The MEC172x is designed to be incorporated into low power PC architecture designs and supports ACPI sleep states

(S0-S5). During normal operation, the hardware always operates in the lowest power state for a given configuration.

The chip power management logic offers two low power states: light sleep and heavy sleep. These features can be used

to support S0 Connected Standby state and the lower ACPI S3-S5 system sleep states. In connected standby, any eSPI

command will wake the device and be processed. When the chip is sleeping, it has many wake events that can be configured

to return the device to normal operation. Some examples of supported wake events are PS2 wake events, RTC,

Week Alarm, Hibernation Timer, or any GPIO pin.

The MEC172x offers a software development system interface that includes a Trace FIFO Debug port, a host accessible

serial debug port with a 16C550A register interface, a Port 80 BIOS Debug Port, and a 2-pin Serial Wire Debug (SWD)

interface. Also included is a 4-wire JTAG interface used for Boundary Scan testing.

The MEC172x also supports eSPI host interface, with Master attached Flash and Slave attached Flash Sharing in the 144 pin package

Security Features

? Boot ROM Secure Boot Loader

- Hardware Root of Trust (RoT) using Secure

Boot and Immutable code

- Supports 2 Code Images in external SPI

Flash (Primary and Fall back image)

- Authenticates SPI Flash image before loading

- Support AES-256 Encrypted SPI Flash

images

? Hardware Accelerators:

- Multi purpose AES Crypto Engine:

- Support for 128-bit - 256-bit key length

- Supports Battery Authentication applications

- Digital Signature Algorithm Support

- Support for ECDSA and EC_KCDSA

- Cryptographic Hash Engine

- Support for SHA-1, SHA-256 to SHA-512

- Public Key Crypto Engine

- Hardware support for RSA and Elliptic

Curve asymmetric public key algorithms

- RSA keys length of 1024 to 4096 bits

- ECC Prime Field keys up to 571 bits

- ECC Binary Field keys up to 571 bits

- Microcoded support for standard public

key algorithms

- OTP for storing Keys and IDs

- Lockable on 32 B boundaries to prevent

read access or write access

- True Random Number Generator

- 1 Kbit FIFO

- JTAG Disabled by default

Peripheral Features

? Internal DMA Controller

- Hardware or Firmware Flow Control

- Firmware Initiated Memory-to-Memory transfers

- Hardware CRC-32 Generator on Channel 0

- 16-Hardware DMA Channels support five

SMBus Master/Slave Controllers, One Quad

SPI Controller and Two General purpose SPI

Controllers

? I2C/SMBus Controllers

- 5 I2C/SMBus controllers

- Up to 16 Configurable I2C ports

- Full Crossbar switch allows any port to be

connected to any controller

- Supports Promiscuous mode of operation

- Fully Operational on Standby Power

- Multi-Master Capable

- Supports Clock Stretching

- Programmable Bus Speeds

- 1 MHz Capable

- Supports DMA Network Layer

? General Purpose I/O Pins

- Inputs:

- Asynchronous rising and falling edge

wakeup detection Interrupt High or Low Level

- Outputs:

- Push Pull or Open Drain output

- Programmable power well emulation

- Pull up or pull down resistor control

- Automatically disabling pull-up resistors

when output driven low

- Automatically disabling pull-down resistors

when output driven high

- Programmable drive strength

- Two separate1.8V/3.3V configurable IO

regions

- Group or individual control of GPIO data

- 13- Over voltage tolerant GPIO pins

- Glitch protection and Under-Voltage Protection

on all GPIO pins

- 8 GPIO Pass through ports

? Input Capture and Compare timer

- Six 32-bit Capture Registers

- 16 Input Pins (ICTx)

- Full Crossbar switch allows any port to be

connected to any controller

- 32-bit Free-running timer

- Two 32-bit Compare Registers

- Capture, Compare and Overflow Interrupts

? Universal Asynchronous Receiver Transmitter

(UART)

- Two High Speed NS16C550A Compatible

UARTs with Send/Receive 16-Byte FIFOs

- UART0 - Configurable 2-pin/4-pin/8-pin

- UART1 - Configurable 2-pin/4-pin/8-pin

- Programmable Main Power or Standby

Power Functionality

- Standard Baud Rates to 115.2 Kbps, Custom

Baud Rates to 1.5 Mbps

? Programmable Timer Interface

- Two16-bit Auto-reloading Timer Instances

- 16 bit Pre-Scale divider

- Halt and Reload control

- Auto Reload

- Two 32-bit Auto-reloading Timer Instances

- 16 bit Pre-Scale divider

- Halt and Reload control

- Auto Reload

- Three Operating Modes per Instance: Timer

(Reload or Free-Running) or One-shot.

- Event Mode is not supported

? 32-bit RTOS Timer

- Runs Off 32kHz Clock Source

- Continues Counting in all the Chip Sleep

States regardless of Processor Sleep State

- Counter is Halted when Embedded Controller

is Halted (e.g., JTAG debugger active, break

points)

- Generates wake-capable interrupt event

? Watch Dog Timer (WDT)

- Watchdog reset IRQ vector

? Embedded Reset Engine

- Resets the EC if external VCI_IN0# pin is

held low for a programmed time

? Upto 13 Programmable Pulse Width Modulator

(PWM) outputs

- Multiple Clock Rates

- 16-Bit ON & 16-Bit OFF Counters

? 4 Fan Tachometer Inputs

- 16 Bit Resolution

? Two RPM-Based Fan Speed Controllers

- Each includes one Tach input and one PWM

output

- Each includes one Tach input and one PWM

output

- 3 accurate from 500 RPM to 16k RPM

- Automatic Tachometer feedback

- Aging Fan or Invalid Drive Detection

- Spin Up Routine

- Ramp Rate Control

- RPM based Fan Control Algorithm

? Breathing LED Interface

- 4 Blinking/Breathing LEDs

- Programmable Blink Rates

- Piecewise Linear Breathing LED Output Controller

- Provides for programmable rise and fall

waveforms

- Operational in EC Sleep States

? Optional support for Physically Unclonable Function

(PUF)

- 2K Byte memory reserved for PUF.

? PS2 Controller

- One PS2 controllers

- Two PS2 ports

- Both ports are 5 volt tolerant

? PROCHOT interface with Two instances of the

PowerGuard Technology

- Monitor for single assertions or cumulative

PROCHOT active time

- Interrupt generation for PROCHOT assertion

events

- Support PROCHOT assertions to external

CPU

- PowerGuard Technology monitors total system

power via dedicated Fast A/D converter

- Two programmable thresholds with hysteresis

and filtering for each V_ISYS input

- Integrated with PROCHOT interface to provide

CPU throttling

- Fast programmable response on high threshold

- Programmable delayed response on low

threshold

? Microchip BC-Link Interconnection Bus

- One HIgh/Low speed Bus master controller

? 3 RC-ID ports

- Single pin interface to External Inexpensive

RC circuit

- Replacement for Multiple GPIOs

- Provides 8 quantized states on One pin

Analog Features

? ADC Interface

- 10-bit or 12-bit readings supported

- ADC Conversion time 500nS/channel

- Upto 16 Channels

- External voltage reference

- Supports thermistor temperature readings

? Two Analog Comparators

- May be used for Hardware Shutdown

- Detection of voltage limit event

- Detection of Thermistor Over-Temp Event

Debug Features

? 2-pin Serial Wire Debug (SWD) interface

? 4-Pin JTAG interface for Boundary Scan

? 1-Pin ITM interface

? Trace FIFO Debug Port (TFDP)