MC88920DW中文資料摩托羅拉數(shù)據(jù)手冊(cè)PDF規(guī)格書

Low Skew CMOS PLL Clock Driver With Power–Down/Power–Up Feature

The MC88920 Clock Driver utilizes phase–locked loop technology to lock its low skew outputs’ frequency and phase onto an input reference clock. It is designed to provide clock distribution for CISC microprocessor or single processor RISC systems. The RST_IN/RST_OUT(LOCK) pins provide a processor reset function designed specifically for the MC68/EC/LC030/040 microprocessor family.

The PLL allows the the high current, low skew outputs to lock onto a single clock input and distribute it with essentially zero delay to multiple locations on a board. The PLL also allows the MC88920 to multiply a low frequency input clock and distribute it locally at a higher (2X) system frequency.

? 2X_Q Output Meets All Requirements of the 20 and 25MHz 68040 Microprocessor PCLK Input Specifications

? Three Outputs (Q0–Q2) With Output–Output Skew <500ps and Six Outputs Total (Q0–Q2, Q3, 2X_Q,) With <1ns Skew Each Being Phase and Frequency Locked to the SYNC Input

? The Phase Variation From Part–to–Part Between SYNC and the ‘Q’ Outputs Is Less Than 600ps (Derived From the TPD Specification, Which Defines the Part–to–Part Skew)

? SYNC Input Frequency Range From 5MHZ to 2X_Q FMax/4

? Additional Outputs Available at 2X and ÷2 the System ‘Q’ Frequency. Also a Q (180° Phase Shift) Output Available.

? All Outputs Have ±36mA Drive (Equal High and Low) CMOS Levels. Can Drive Either CMOS or TTL Inputs. All Inputs Are TTL–Level Compatible

? Test Mode Pin (PLL_EN) Provided for Low Frequency Testing

? Special Power–Down Mode With 2X_Q, Q0, and Q1 Being Reset (With MR), and Other Outputs Remain Running. 2X_Q, Q0 and Q1 Are Guaranteed to Be in Lock 3 Clock Cycles After MR Is Negated