Description

The MC10E/100E167 contains six 2:1 multiplexers followed by D flip-flops with single-ended outputs. Input data are selected by the Select control, SEL. The selected data are transferred to the flip-flop outputs by a positive edge on CLK1 or CLK2 (or both). A HIGH on the Master Reset (MR) pin asynchronously forces all Q outputs LOW.

Features

The 100 Series contains temperature compensation.

? 1000 MHz Min. Operating Frequency

? 800 ps Max. Clock to Output

? Single-Ended Outputs

? Asynchronous Master Resets

? Dual Clocks

? PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V

? NECL Mode Operating Range: VCC = 0 V with VEE = ?4.2 V to ?5.7 V

? Internal Input 50 kΩ Pulldown Resistors

? ESD Protection: Human Body Model; > 2 kV,

Machine Model; > 200 V

Charged Device Model; > 2 kV

? Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

? Moisture Sensitivity Level:

Pb = 1

Pb?Free = 3

For Additional Information, see Application Note AND8003/D

? Flammability Rating: UL 94 V?0 @ 0.125 in, Oxygen Index: 28 to 34

? Transistor Count = 323 devices

? Pb?Free Packages are Available*

MC10E167屬于集成電路（IC） > 信號開關(guān)，多路復(fù)用器，解碼器。安森美半導(dǎo)體公司制造生產(chǎn)的MC10E167信號開關(guān)，多路復(fù)用器，解碼器邏輯型信號開關(guān)、多路復(fù)用器和編碼器 IC 可用于對以數(shù)字格式表示數(shù)據(jù)的電信號進行路由和選擇。這些器件與設(shè)計用于模擬信號的類似產(chǎn)品有所不同，它們保留的信息表示為兩個電狀態(tài)之一，而不是兩個外部界限內(nèi)的無窮變化量。