MAX9000中文資料阿爾特數(shù)據(jù)手冊PDF規(guī)格書

General Description

The MAX 9000 family of in-system-programmable, high-density, highperformance EPLDs is based on Altera’s third-generation MAX architecture. Fabricated on an advanced CMOS technology, the EEPROMbased MAX 9000 family provides 6,000 to 12,000 usable gates, pin-to-pin delays as fast as 10 ns, and counter speeds of up to 144 MHz. The -10 speed grade of the MAX 9000 family is compliant with the PCI Local Bus Specification, Revision 2.2. Table 3 shows the speed grades available for MAX 9000 devices.

Features...

■ High-performance CMOS EEPROM-based programmable logic

devices (PLDs) built on third-generation Multiple Array MatriX

(MAX?) architecture

■ 5.0-V in-system programmability (ISP) through built-in IEEE Std.

1149.1 Joint Test Action Group (JTAG) interface

■ Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE

Std. 1149.1-1990

■ High-density erasable programmable logic device (EPLD) family

ranging from 6,000 to 12,000 usable gates (see Table 1)

■ 10-ns pin-to-pin logic delays with counter frequencies of up to

144 MHz

■ Fully compliant with the peripheral component interconnect Special

Interest Group’s (PCI SIG) PCI Local Bus Specification, Revision 2.2

■ Dual-output macrocell for independent use of combinatorial and

registered logic

■ FastTrack? Interconnect for fast, predictable interconnect delays

■ Input/output registers with clear and clock enable on all I/O pins

■ Programmable output slew-rate control to reduce switching noise

■ MultiVolt? I/O interface operation, allowing devices to interface with

3.3-V and 5.0-V devices

■ Configurable expander product-term distribution allowing up to 32

product terms per macrocell

■ Programmable power-saving mode for more than 50 power

reduction in each macrocell

■ Programmable macrocell flipflops with individual clear, preset,

clock, and clock enable controls

■ Programmable security bit for protection of proprietary designs

■ Software design support and automatic place-and-route provided by

Altera’s MAX+PLUS? II development system on Windows-based

PCs as well as Sun SPARCstation, HP 9000 Series 700/800, and IBM

RISC System/6000 workstations

■ Additional design entry and simulation support provided by EDIF

2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),

Verilog HDL, VHDL, and other interfaces to popular EDA tools from

manufacturers such as Cadence, Exemplar Logic, Mentor Graphics,

OrCAD, Synopsys, Synplicity, and VeriBest

■ Programming support with Altera’s Master Programming Unit

(MPU), BitBlasterTM serial download cable, ByteBlasterTM parallel

port download cable, and ByteBlasterMVTM parallel port download

cable, as well as programming hardware from third-party

manufacturers

■ Offered in a variety of package options with 84 to 356 pins (see

Table 2)