M470L6423EN0-CLB3中文資料三星數(shù)據(jù)手冊PDF規(guī)格書

Feature

? Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V

? Double-data-rate architecture; two data transfers per clock cycle

? Bidirectional data strobe(DQS)

? Differential clock inputs(CK and CK)

? DLL aligns DQ and DQS transition with CK transition

? Programmable Read latency 2, 2.5 (clock)

? Programmable Burst length (2, 4, 8)

? Programmable Burst type (sequential & interleave)

? Edge aligned data output, center aligned data input

? Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)

? Serial presence detect with EEPROM

? PCB : Height 1,250 (mil), double (512MB) sided

? SSTL_2 Interface

? 54pin sTSOP(II)-300 package