M36W108AT120ZM6T中文資料意法半導(dǎo)體數(shù)據(jù)手冊PDF規(guī)格書

DESCRIPTION

The M36W108A is multi-chip device containing an 8 Mbit boot block Flash memory and a 1 Mbit of SRAM. The device is offered in the new Chip Scale Package solutions: LBGA48 1.0mm ball pitch and LGA48 1.0mm land pitch.

■ SUPPLY VOLTAGE

– VCCF = VCCS = 2.7V to 3.6V: for Program, Erase and Read

■ ACCESS TIME: 100ns

■ LOW POWER CONSUMPTION

– Read: 40mA max. (SRAM chip)

– Stand-by: 30μA max. (SRAM chip)

– Read: 10mA max. (Flash chip)

– Stand-by: 100μA max. (Flash chip)

FLASH MEMORY

■ 8 Mbit (1Mb x 8) BOOT BLOCK ERASE

■ PROGRAMMING TIME: 10μs typical

■ PROGRAM/ERASE CONTROLLER (P/E.C.)

– Program Byte-by-Byte

– Status Register bits and Ready/Busy Output

■ SECURITY PROTECTION MEMORY AREA

■ INSTRUCTION ADDRESS CODING: 3 digits

■ MEMORY BLOCKS

– Boot Block (Top or Bottom location)

– Parameter and Main Blocks

■ BLOCK, MULTI-BLOCK and CHIP ERASE

■ ERASE SUSPEND and RESUME MODES

– Read and Program another Block during Erase Suspend

■ 100,000 PROGRAM/ERASE CYCLES per BLOCK

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h

– Device Code, M36W108AT: D2h

– Device Code, M36W108AB: DCh

SRAM

■ 1 Mbit (128Kb x 8)

■ POWER DOWN FEATURES USING TWO CHIP ENABLE INPUTS

■ LOW VCC DATA RETENTION: 2V