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LMX1906-SP中文資料德州儀器數(shù)據(jù)手冊(cè)PDF規(guī)格書

LMX1906-SP
廠商型號(hào)

LMX1906-SP

功能描述

LMX1906-SP Space Grade Low-Noise, High-Frequency JESD204B/C Buffer, Multiplier and Divider

文件大小

2.9657 Mbytes

頁面數(shù)量

72

生產(chǎn)廠商 Texas Instruments
企業(yè)簡稱

TI1德州儀器

中文名稱

德州儀器官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

更新時(shí)間

2025-1-7 20:00:00

LMX1906-SP規(guī)格書詳情

1 Features

? SMD #5962-23202

– Total ionizing dose 100 krad (ELDRS-free)

– Single event latch-up (SEL) immune up to 87

MeV - cm2 /mg

– Single event functional interrupt (SEFI) immune

up to 87 MeV - cm2 /mg

? Clock buffer for 300-MHz to 15-GHz frequency

? Ultra-Low Noise

– Noise floor of –159 dBc/Hz at 6-GHz output

– 36-fs additive jitter (100 Hz to fCLK) at 6-GHz

output

– 5-fs additive jitter (100 Hz - 100 MHz)

? 4 high-frequency clocks with corresponding

SYSREF outputs

– Shared divide by 1 (Buffer), 2, 3, 4, 5, 6, 7, and

8

– Shared programmable multiplier x2, x3, and x4

? Support pin mode options to configure the device

without SPI

? LOGICLK output with corresponding SYSREF

output

– On separate divide bank

– 1, 2, 4 pre-divider

– 1 (bypass), 2, …, 1023 post divider

? 8 programmable output power levels

? Synchronized SYSREF clock outputs

– 508 delay step adjustments of less than 2.5 ps

each at 12.8 GHz

– Generator and repeater modes

– Windowing feature for SYSREFREQ pins to

optimize timing

? SYNC feature to all divides and multiple devices

? 2.5-V operating voltage

? –55oC to +125oC operating temperature

2 Applications

? Radar imaging payload

? Communications payloads

? Command and data handling

? Data converter clocking

? Clock distribution/multiplication/division

3 Description

The LMX1906-SP is an buffer, divider and multiplier

that features high frequency, ultra-low jitter, and

SYSREF outputs. This device combined with an ultralow

noise reference clock source is an exemplary

solution for clocking data converters, especially when

sampling above 3 GHz. Each of the 4 high frequency

clock outputs and additional LOGICLK output is

paired with a SYSREF output clock signal. The

SYSREF signal for JESD interfaces can either be

internally generated or passed in as an input and

re-clocked to the device clocks. This device can

distribute the mutlichannel, low skew, ultra-low noise

local oscillator signals to multiple mixers by disabling

the SYSREF outputs.

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