K7P403623B中文資料三星數(shù)據(jù)手冊PDF規(guī)格書

FUNCTION DESCRIPTION

The K7P403623B andK7P401823B are 4,718,592 bit Synchronous SRAM. It is organized as 131,072 words of 36 bits(or 262,144 words of 18 bits) and is implemented in SAMSUNGs advanced CMOS technology.

Single differential PECL level K clocks or single ended or differential LVCMOS/LVTTL clock are used to initiate the read/write operation and all internal operations are self-timed. At the rising edge of K clock, all addresses, Write Enables, Synchronous Select and Data Ins are registered internally. Data outputs are updated from output latches of the falling edge of K clock. An internal write data buffer allows write data to follow one cycle after addresses and controls. The package is 119(7x17) Ball Grid Array with balls on a 1.27mm pitch.

FEATURES

? 128Kx36 or 256Kx18 Organizations.

? 3.3V VDD, 2.5/3.3V VDDQ.

? LVTTL 2.5/3.3V Input and Output Levels.

? Differential, PECL clock / Single ended or differential LVTTL clock Inputs

? Synchronous Read and Write Operation

? Registered Input and Latched Output

? Internal Pipeline Latches to Support Late Write.

? Byte Write Capability(four byte write selects, one for each 9 bits)

? Synchronous or Asynchronous Output Enable.

? Power Down Mode via ZZ Signal.

? JTAG 1149.1 Compatible Test Access port.

? 119(7x17) Pin Ball Grid Array Package(14mmx22mm).