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ISPLSI1032-60LTI中文資料萊迪思數(shù)據(jù)手冊(cè)PDF規(guī)格書

廠商型號(hào) |
ISPLSI1032-60LTI |
功能描述 | In-System Programmable High Density PLD |
文件大小 |
236.85 Kbytes |
頁(yè)面數(shù)量 |
16 頁(yè) |
生產(chǎn)廠商 | Lattice Semiconductor |
企業(yè)簡(jiǎn)稱 |
Lattice【萊迪思】 |
中文名稱 | 萊迪思半導(dǎo)體公司官網(wǎng) |
原廠標(biāo)識(shí) | ![]() |
數(shù)據(jù)手冊(cè) | |
更新時(shí)間 | 2025-4-25 13:01:00 |
人工找貨 | ISPLSI1032-60LTI價(jià)格和庫(kù)存,歡迎聯(lián)系客服免費(fèi)人工找貨 |
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ISPLSI1032-60LTI規(guī)格書詳情
Description
The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1032 features 5-Volt insystem programming and in-system diagnostic capabilities. It is the first device which offers non-volatile on-the-fly reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. It is architecturally and parametrically compatible to the pLSI 1032 device, but multiplexes four of the dedicated input pins to control in-system programming.
Features
? HIGH-DENSITY PROGRAMMABLE LOGIC
— High Speed Global Interconnect
— 6000 PLD Gates
— 64 I/O Pins, Eight Dedicated Inputs
— 192 Registers
— Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.
— Small Logic Block Size for Fast Random Logic
— Security Cell Prevents Unauthorized Copying
? HIGH PERFORMANCE E2CMOS? TECHNOLOGY
— fmax = 90 MHz Maximum Operating Frequency
— fmax = 60 MHz for Industrial and Military/883 Devices
— tpd = 12 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile E2CMOS Technology
— 100 Tested
? ispLSI OFFERS THE FOLLOWING ADDED FEATURES
— In-System Programmable? (ISP?) 5-Volt Only
— Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
? COMBINES EASE OF USE AND THE FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue Logic and Structured Designs
— Four Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global Interconnectivity
? ispLSI AND pLSI DEVELOPMENT TOOLS
pDS? Software
— Easy to Use PC Windows? Interface
— Boolean Logic Compiler
— Manual Partitioning
— Automatic Place and Route
— Static Timing Table
ispDS+? Software
— Industry Standard, Third Party Design Environments
— Schematic Capture, State Machine, HDL
— Automatic Partitioning and Place and Route
— Comprehensive Logic and Timing Simulation
— PC and Workstation Platforms
產(chǎn)品屬性
- 型號(hào):
ISPLSI1032-60LTI
- 功能描述:
CPLD - 復(fù)雜可編程邏輯器件 USE ispMACH 4000V
- RoHS:
否
- 制造商:
Lattice
- 存儲(chǔ)類型:
EEPROM
- 大電池?cái)?shù)量:
128
- 最大工作頻率:
333 MHz
- 延遲時(shí)間:
2.7 ns
- 可編程輸入/輸出端數(shù)量:
64
- 工作電源電壓:
3.3 V
- 最大工作溫度:
+ 90 C
- 最小工作溫度:
0 C
- 封裝/箱體:
TQFP-100
供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
---|---|---|---|---|---|---|---|
Lattice Semiconductor Corporat |
21+ |
100-LQFP |
90 |
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詢價(jià) | ||
LATTICE |
23+ |
TQFP100 |
7000 |
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LATTICE/萊迪斯 |
24+ |
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12000 |
原裝 |
詢價(jià) | ||
LATTICE |
2138+ |
QFP |
8960 |
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詢價(jià) | ||
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3000 |
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詢價(jià) | ||
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3600 |
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詢價(jià) | ||
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詢價(jià) | ||
LLATTICE |
2447 |
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詢價(jià) | ||
LLT |
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42443 |
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詢價(jià) | |||
Lattice |
2318+ |
QFP-100 |
4980 |
Lattice全系列進(jìn)口原裝特價(jià) |
詢價(jià) |